LM5045 datasheet(3/38 Pages) TI

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LM5045

www.ti.com

SNVS699G – FEBRUARY 2011 – REVISED MARCH 2013

PIN DESCRIPTIONS

HTSSOP

WQFN

Name

Description

Application Information

UVLO

Line Under-Voltage Lockout

An external voltage divider from the power source sets the

shutdown and standby comparator levels. When UVLO reaches the

0.4V threshold the VCC and REF regulators are enabled. At the

1.25V threshold, the SS pin is released and the controller enters the

active mode. Hysteresis is set by an internal current sink that pulls

20µA from the external resistor divider.

OVP/OTP

Over Voltage Protection

An external voltage divider from the input power supply sets the

shutdown level during an over-voltage condition. Alternatively, an

external NTC thermistor voltage divider can be used to set the

shutdown temperature. The threshold is 1.25V. Hysteresis is set by

an internal current that sources 20 µA of current into the external

resistor divider.

RAMP

Input to PWM Comparator

Modulation ramp for the PWM comparator. This ramp can be a

signal representative of the primary current (current mode) or

proportional to the input voltage (feed-forward voltage mode). This

pin is reset to GND at the end of every cycle.

Current Sense Input

If CS exceeds 750mV the PWM output pulse will be terminated,

entering cycle-by-cycle current limit. An internal switch holds CS low

for 40nS after either output switches high to blank leading edge

transients.

SLOPE

Slope Compensation Current

A ramping current source from 0 to 100µA is provided for slope

compensation in current mode control. This pin can be connected

through an appropriate resistor to the CS pin to provide slope

compensation. If slope compensation is not required, SLOPE must

be tied to ground.

COMP

Input to the Pulse Width Modulator

An external opto-coupler connected to the COMP pin sources

current into an internal NPN current mirror. The PWM duty cycle is

at maximum with zero input current, while 1mA reduces the duty

cycle to zero. The current mirror improves the frequency response

by reducing the AC voltage across the opto-coupler.

REF

Output of a 5V reference

Maximum output current is 15mA. Locally decouple with a 0.1µF

capacitor.

RT/SYNC

Oscillator Frequency Control and

The resistance connected between RT and AGND sets the

Frequency Synchronization

oscillator frequency. Synchronization is achieved by AC coupling a

pulse to the RT/SYNC pin that raises the voltage at least 1.5V

above the 2V nominal bias level.

AGND

Analog Ground

Connect directly to the Power Ground.

RD1

Synchronous Rectifier Leading

The resistance connected between RD1 and AGND sets the delay

Edge Delay

from the falling edge of SR1 or SR2 and the rising edge of

HO2/LO1 or HO1/LO2 respectively.

RD2

Synchronous Rectifier Trailing

The resistance connected between RD2 and AGND sets the delay

Edge Delay

from the falling edge of HO1/LO2 or HO2/LO1 and the rising edge

of SR2 or SR1 respectively.

RES

Restart Timer

Whenever the CS pin exceeds the 750mV cycle-cycle current limit

threshold, 30µA current is sourced into the RES capacitor for the

remainder of the PWM cycle. If the RES capacitor voltage reaches

1.0V, the SS capacitor is discharged to disable the HO1, HO2, LO1,

LO2 and SR1, SR2 outputs. The SS pin is held low until the voltage

on the RES capacitor has been ramped between 2V and 4V eight

times by 10µA charge and 5µA discharge currents. After the delay

sequence, the SS capacitor is released to initiate a normal start-up

sequence.

Soft-Start Input

An internal 20µA current source charges the SS pin during start-up.

The input to the PWM comparator gradually rises as the SS

capacitor charges to steadily increase the PWM duty cycle. Pulling

the SS pin to a voltage below 200mV stops PWM pulses at HO1,2

and LO1,2 and turns off the synchronous rectifier FETs to a low

state.

SSSR

Secondary Side Soft-Start

An external capacitor and an internal 20µA current source set the

soft-start ramp for the synchronous rectifiers. The SSSR capacitor

charge-up is enabled after the first output pulse and SS>2V and

Icomp <800µA

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