AD5504 datasheet(6/20 Pages) AD

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AD5504

Data Sheet

Rev. B | Page 6 of 20

TIMING CHARACTERISTICS

VDD = 30 V, VLOGIC = 2.3 V to 5.5 V and −40°C < TA < +105°C; all specifications TMIN to TMAX, unless otherwise noted.

Table 4.

Parameter

Limit1

Unit

Test Conditions/Comments

t12

ns min

SCLK cycle time

ns min

SCLK high time

ns min

SCLK low time

ns min

SYNC falling edge to SCLK rising edge setup time

ns min

Data setup time

ns min

Data hold time

ns min

SCLK falling edge to SYNC rising edge

ns min

Minimum SYNC high time

ns min

LDAC pulse width low

t10

ns min

SCLK falling edge to LDAC rising edge

t11

ns min

CLR pulse width low

t12

100

ns typ

CLR pulse activation time

t13

μs typ

ALARM clear time

t14

110

ns min

SCLK cycle time in read mode

t153

ns max

SCLK rising edge to SDO valid

t163

ns min

SCLK to SDO data hold time

t174

μs max

Power-on reset time (this is not shown in the timing diagrams)

t185

μs max

Power-on time (this is not shown in the timing diagrams)

t19

μs typ

ALARM clear to output amplifier turn on (this is not shown in the timing

diagrams)

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

Maximum SCLK frequency is 16.667 MHz.

Under load conditions shown in Figure 2.

Time from when the VDD/VLOGIC supplies are powered-up to when a digital interface command can be executed.

Time required from execution of power-on software command to when the DAC outputs have settled to 1 V.

VOH (MIN) – VOL (MAX)

200µA

IOL

200µA

IOH

TO OUTPUT

50pF

Figure 2. Load Circuit for SDO Timing Diagram

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