AD5504 datasheet(14/20 Pages) AD

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AD5504

Data Sheet

Rev. B | Page 14 of 20

THEORY OF OPERATION

The AD5504 contains four DACs, four output amplifiers, and a

precision reference in a single package. The architecture of a

single DAC channel consists of a 12-bit resistor string DAC

followed by an output buffer amplifier. The part operates from

a single-supply voltage of 10 V to 62 V. The DAC output voltage

range is selected via the range select, R_SEL, pin. The DAC

output range is 0 V to 30 V if R_SEL is held high and 0 V to

60 V if R_SEL is held low. Data is written to the AD5504 in a

16-bit word format (see Table 8), via a serial interface.

POWER-UP STATE

On power-up, the power-on reset circuitry clears the bits of the

control register to 0x40 (see Table 10). This ensures that the

analog section is initially powered down, which helps reduce

power consumption. The user can program the DAC registers

to the required values while typically consuming only 30 µA of

supply current. The power-on reset circuitry also ensures that

all the input and DAC registers power up in a known condition,

0x000, and remain there until a valid write to the device has

taken place. The analog section can be powered up by setting

any or all of Bit C2 to Bit C5 of the control register to 1.

POWER-DOWN MODE

Each DAC channel can be individually powered up or powered

down by programming the control register (see Table 10).

When the DAC channel is powered down, the associated analog

circuitry turns off to reduce power consumption. The digital

section of the AD5504 remains powered up. The output of the

DAC amplifier can be three-stated or connected to AGND via

an internal 20 kΩ resistor, depending on the state of Bit C6 in

the control register. The power-down mode does not change the

contents of the DAC register to ensure that the DAC channel

returns to its previous voltage when the power-down bit is set to 1.

The AD5504 also offers the user the flexibility of updating the

DAC registers during power-down. The control register can be

read back at any time to check the status of the bits.

DAC CHANNEL ARCHITECTURE

The architecture of a single DAC channel consists of a 12-bit

resistor string DAC followed by an output buffer amplifier (see

Figure 17). The resistor string section is simply a string of

resistors, each of Value R from VREF generated by the precision

reference to AGND. This type of architecture guarantees DAC

monotonicity. The 12-bit binary digital code loaded to the DAC

tapped off before being fed into the output amplifier. The

output amplifier multiplies the DAC output voltage to give a

fixed linear voltage output range of 0 V to 60 V if R_SEL = 0

or 0 V to 30 V if R_SEL = 1. Each output amplifier is capable

of driving a 60 kΩ load while allowing an output swing within

the range of AGND + 0.5 V and VDD − 0.5 V.

Because the DAC architecture gives a fixed voltage output range

of 0 V to 30 V or 0 V to 60 V, the user should set VDD to at least

30.5 V or 60.5 V to use the maximum DAC resolution. The data

format for the AD5501 is straight binary and the output voltage

follows the formula

Range

VOUT

4096

where:

D is the code loaded to the DAC.

Range = 30, if R_SEL is high, and 60 if R_SEL is low.

GAIN

VOUTx

DAC

INPUT

PRECISION

REFERENCE

AGND

DAC

Figure 17. DAC Channel Architecture (Single-Channel Shown)

SELECTING THE OUTPUT RANGE

The output range of the DACs is selected by the R_SEL pin.

When the R_SEL pin is connected to Logic 1, the DAC output

voltages can be set between 0 V and 30 V. When the R_SEL pin

is connected to Logic 0, the DAC output voltages can be set

between 0 V and 60 V. The state of R_SEL can be changed any

time when the serial interface is not being used, that is, not

during a read or write operation. When the R_SEL pin is

changed, the voltage on the output pin remains the same until

the next write to the DAC register (and LDAC is brought low).

For example, if the user writes 0x800 to the DAC register when

in 30 V mode (R_SEL = 1), the output voltage is 15 V (assuming

LDAC is low or has been pulsed low). When the user switches

to 60 V mode (R_SEL = 0), the output stays at 15 V until the

user writes a new value to the DAC register. LDAC must be low

or be pulsed low for the output to change.

CLR FUNCTION

The AD5504 has a hardware CLR pin that is an asynchronous

clear input. The CLR input is falling edge sensitive. Bringing the

CLR line low clears the contents of the input register and the

DAC registers to 0x000. The CLR pulse activation time, that is,

the falling edge of CLR to when the output starts to change, is

typically 100 ns.

LDAC FUNCTION

The DAC outputs can be updated using the hardware LDAC

pin. LDAC is normally high. On the falling edge of LDAC, data

is copied from the input registers to the DAC registers, and the

DAC outputs are updated simultaneously (asynchronous update

mode, see Figure 3). If the LDAC is kept low, or is low on the

falling edge of the 16th SCLK, the appropriate DAC register and

DAC output are updated automatically (synchronous update

mode, see Figure 3).

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