17

Figure 16. Series LED drive with open collector gate (4.7 k resistor shunts I

Figure 14. LSTTL to CMOS interface circuit.

HCPL-2201 fig 15

1

8

2

7

3

6

4

5

HCPL-2201/11

HCPL-02XX

HCNW22XX

DATA

INPUT

D1 (1N4150) REQUIRED FOR

ACTIVE PULL-UP DRIVER.

1.1 k

Ω

VCC1 (+5 V)

VCC

GND

D1

TTL or

LSTTL

Figure 15. Alternative LED drive circuit.

120 pF*

HCPL-2201 fig 16

1

8

2

7

3

6

4

5

HCPL-2201/11

HCPL-02XX

HCNW22XX

DATA INPUT

TTL OR LSTTL

1.1 k

Ω

80

Ω*

VCC (+5 V)

OPEN

COLLECTOR

GATE

* 120 pF PEAKING CAPACITOR

MAY BE OMITTED AND 80

Ω

RESISTOR MAY BE SHORTED

WHERE 500 ns PROPAGATION

DELAY IS SUFFICIENT.

VCC

GND

4.7 k

Ω

Figure 13b. Recommended LSTTL to LSTTL circuit for applications requiring a maximum allowable propagation delay of 300 ns.

120 pF

HCPL-2201 fig 13b

1

8

2

7

3

6

4

5

1

2

HCPL-2201/11

HCPL-02XX

HCNW22XX

DATA INPUT

TTL OR LSTTL

VCC2 (+5 V)

UP TO 16 LSTTL LOADS

OR 4 TTL LOADS

*

* 0.1 µF BYPASS

1.1 k

Ω

80

Ω

VCC1 (+5 V)

DATA OUTPUT

120 pF*

HCPL-2201 fig 14

1

8

2

7

3

6

4

5

1

2

HCPL-2201/11

HCPL-02XX

HCNW22XX

DATA INPUT

TTL OR LSTTL

VCC2

(4.5 TO 20 V)

**0.1 µF BYPASS

1.1 k

Ω

80

Ω*

VCC1 (+5 V)

DATA OUTPUT

TOTEM

POLE

OUTPUT

GATE

* 120 pF PEAKING CAPACITOR

MAY BE OMITTED AND 80

Ω

RESISTOR MAY BE SHORTED

WHERE 500 ns PROPAGATION

DELAY IS SUFFICIENT.

VCC

GND

CMOS

VCC2

5 V

10 V

15 V

20 V

RL

1.1 k

Ω

2.37 k

Ω

3.83 k

Ω

5.11 k

Ω

RL

**