DM163006 datasheet(144/320 Pages) MICROCHIP

144 / 320 page

PIC18C601/801

DS39541A-page 144

Advance Information

 2001 Microchip Technology Inc.

14.4

Compare Mode

In Compare mode, the 16-bit CCPR1 (CCPR2) register

value is constantly compared against either the TMR1

When a match occurs, the RC2/CCP1 (RC1/CCP2) pin

can have one of the following actions:

• Driven high

• Driven low

• Toggle output (high to low or low to high)

• Remains unchanged

The action on the pin is based on the value of control

bits CCP1M3:CCP1M0 (CCP2M3:CCP2M0). At the

same time, interrupt flag bit CCP1IF (CCP2IF) is set.

14.4.1

CCP PIN CONFIGURATION

The user must configure the CCPx pin as an output by

clearing the appropriate TRISC bit.

14.4.2

TIMER1/TIMER3 MODE SELECTION

Timer1 and/or Timer3 must be running in Timer mode,

or Synchronized Counter mode, if the CCP module is

using the compare feature. In Asynchronous Counter

mode, the compare operation may not work.

14.4.3

SOFTWARE INTERRUPT MODE

When Generate Software Interrupt is chosen, the

CCP1 pin is not affected. Only a CCP interrupt is gen-

erated (if enabled).

14.4.4

SPECIAL EVENT TRIGGER

In this mode, an internal hardware trigger is generated,

which may be used to initiate an action.

The special event trigger output of CCP1 resets the

TMR1 register pair. This allows the CCPR1 register to

effectively be a 16-bit programmable period register for

Timer1.

The special trigger output of CCPx resets either the

TMR1, or TMR3 register pair. Additionally, the CCP2

Special Event Trigger will start an A/D conversion, if the

A/D module is enabled.

FIGURE 14-2:

COMPARE MODE OPERATION BLOCK DIAGRAM

Note:

Clearing the CCP1CON register will force

the RC2/CCP1 compare output latch to the

default low level. This is not the data latch.

Note:

The special event trigger from the CCP2

module will not set the Timer1 or Timer3

interrupt flag bits.

CCPR1H CCPR1L

TMR1H

TMR1L

Comparator

Output

Logic

Special Event Trigger

Set Flag bit CCP1IF

Match

RC2/CCP1

TRISC<2>

CCP1M3:CCP1M0

Mode Select

Output Enable

Special Event Trigger will:

Reset Timer1 or Timer3 (but not set Timer1 or Timer3 Interrupt Flag bit)

Set bit GO/DONE, which starts an A/D conversion (CCP2 only)

TMR3H

TMR3L

T3CCP2

CCPR2H CCPR2L

Comparator

T3CCP2

T3CCP1

Output

Logic

Special Event Trigger

Set Flag bit CCP2IF

Match

RC1/CCP2

TRISC<1>

CCP2M3:CCP2M0

Mode Select

Output Enable

Note:

I/O pins have diode protection to VDD and VSS.

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