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DM163006 Datasheet(PDF) 147 Page - Microchip Technology |
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DM163006 Datasheet(HTML) 147 Page - Microchip Technology |
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147 / 320 page ![]() 2001 Microchip Technology Inc. Advance Information DS39541A-page 147 PIC18C601/801 14.5.3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. Set the PWM period by writing to the PR2 register. 2. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. 3. Make the CCP1 pin an output by clearing the TRISC<2> bit. 4. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. 5. Configure the CCP1 module for PWM operation. TABLE 14-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 25 MHz TABLE 14-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2 PWM Frequency 1.53 kHz 6.10 kHz 24.41 kHz 97.66kHz 195.31 kHz 260.42 kHz Timer Prescaler (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0FFh FFh FFh 3Fh 1Fh 17h Maximum Resolution (bits) 10 10 10 8 7 6.6 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other RESETS INTCON GIE/ GIEH PEIE/ GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP -000 0000 -000 0000 TRISC PORTC Data Direction Register 1111 1111 1111 1111 TMR2 Timer2 Module’s Register 0000 0000 0000 0000 PR2 Timer2 Module’s Period Register 1111 1111 1111 1111 T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu CCP1CON — — DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 PIR2 — — — — BCLIF LVDIF TMR3IF CCP2IF ---- 0000 ---- 0000 PIE2 — — — — BCLIE LVDIE TMR3IE CCP2IE ---- 0000 ---- 0000 IPR2 — — — — BCLIP LVDIP TMR3IP CCP2IP ---- 0000 ---- 0000 Legend: x = unknown, u = unchanged, — = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2. |
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