DM163006 datasheet(151/320 Pages) MICROCHIP

151 / 320 page

 2001 Microchip Technology Inc.

Advance Information

DS39541A-page 151

PIC18C601/801

SSPCON1 REGISTER

R/W-0

WCOL

SSPOV

SSPEN

CKP

SSPM3

SSPM2

SSPM1

SSPM0

bit 7

bit 0

bit 7

WCOL: Write Collision Detect bit

Master mode:

= A write to the SSPBUF register was attempted while the I2C conditions were not valid for a

transmission to be started

= No collision

Slave mode:

= The SSPBUF register is written while it is still transmitting the previous word (must be cleared in

software)

= No collision

bit 6

SSPOV: Receive Overflow Indicator bit

In SPI mode:

= A new byte is received while the SSPBUF register is still holding the previous data. In case of

overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave mode, the

user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master

mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing

to the SSPBUF register. (Must be cleared in software.)

= No overflow

In I2C mode:

= A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a

"don’t care" in Transmit mode. (Must be cleared in software.)

= No overflow

bit 5

SSPEN: Synchronous Serial Port Enable bit

In both modes, when enabled, these pins must be properly configured as input or output.

In SPI mode:

= Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins

= Disables serial port and configures these pins as I/O port pins

In I2C mode:

= Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins

= Disables serial port and configures these pins as I/O port pins

bit 4

CKP: Clock Polarity Select bit

In SPI mode:

= Idle state for clock is a high level

= Idle state for clock is a low level

In I2C Slave mode:

SCK release control

= Enable clock

= Holds clock low (clock stretch). (Used to ensure data setup time.)

In I2C Master mode:

Unused in this mode

bit 3 - 0

SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

0000

= SPI Master mode, clock = FOSC/4

0001

= SPI Master mode, clock = FOSC/16

0010

= SPI Master mode, clock = FOSC/64

0011

= SPI Master mode, clock = TMR2 output/2

0100

= SPI Slave mode, clock = SCK pin. SS pin control enabled.

0101

= SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.

0110

= I2C Slave mode, 7-bit address

0111

= I2C Slave mode, 10-bit address

1000

= I2C Master mode, clock = FOSC / (4 * (SSPADD+1) )

1001

= Reserved

1010

= Reserved

1011

= I2C firmware controlled Master mode (Slave idle)

1100

= Reserved

1101

= Reserved

1110

= I2C Slave mode, 7-bit address with START and STOP bit interrupts enabled

1111

= I2C Slave mode, 10-bit address with START and STOP bit interrupts enabled

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

’1’ = Bit is set

’0’ = Bit is cleared

x = Bit is unknown

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