DM163006 datasheet(154/320 Pages) MICROCHIP

154 / 320 page

PIC18C601/801

DS39541A-page 154

Advance Information

 2001 Microchip Technology Inc.

The MSSP consists of a transmit/receive shift register

(SSPSR) and a buffer register (SSPBUF). The SSPSR

shifts the data in and out of the device, MSb first. The

SSPBUF holds the data that was written to the SSPSR,

until the received data is ready. Once the 8 bits of data

have been received, that byte is moved to the SSPBUF

ters), are set. This double buffering of the received data

(SSPBUF) allows the next byte to start reception before

reading the data that was just received. Any write to the

SSPBUF register during transmission/reception of data

will be ignored, and the write collision detect bit, WCOL

(SSPCON1 register), will be set. User software must

clear the WCOL bit so that it can be determined if the

following write(s) to the SSPBUF register completed

successfully.

When the application software is expecting to receive

valid data, the SSPBUF should be read before the next

byte of data to transfer is written to the SSPBUF. The

buffer full (BF) bit (SSPSTAT register) indicates when

SSPBUF has been loaded with the received data

(transmission is complete). When the SSPBUF is read,

the BF bit is cleared. This data may be irrelevant if the

SPI is only a transmitter. Generally, the MSSP interrupt

is used to determine when the transmission/reception

has completed. The SSPBUF must be read and/or

written. If the interrupt method is not going to be used,

then software polling can be done to ensure that a write

collision does not occur. Example 15-1 shows the

loading of the SSPBUF (SSPSR) for data transmission.

The SSPSR is not directly readable or writable, and

can only be accessed by addressing the SSPBUF reg-

ister. Additionally, the MSSP status register (SSPSTAT

15.3.2

ENABLING SPI I/O

To enable the serial port, SSP enable bit, SSPEN

(SSPCON1 register), must be set. To reset or reconfig-

ure SPI mode, clear the SSPEN bit, re-initialize the

SSPCON registers, and then set the SSPEN bit. This

configures the SDI, SDO, SCK, and SS pins as serial

port pins. For the pins to behave as the serial port func-

tion, corresponding pins must have their data direction

bits (in the TRIS register) appropriately programmed.

That is:

• SDI is automatically controlled by the SPI module

• SDO must have TRISC<5> bit cleared

• SCK (Master mode) must have TRISC<3> bit

cleared

• SCK (Slave mode) must have TRISC<3> bit set

• RA5 must be configured as digital I/O using

ADCON1 register

• SS must have TRISA<5> bit set

Any serial port function that is not desired may be

overridden by programming the corresponding data

direction (TRIS) register to the opposite value.

EXAMPLE 15-1:

LOADING THE SSPBUF (SSPSR) REGISTER

LOOP BTFSS SSPSTAT, BF

;Has data been received (transmit complete)?

BRA

LOOP

;No

MOVF

SSPBUF, W

;WREG reg = contents of SSPBUF

MOVWF RXDATA

;Save in user RAM, if data is meaningful

MOVF

TXDATA, W

;W reg = contents of TXDATA

MOVWF SSPBUF

;New data to xmit

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