DM163006 datasheet(159/320 Pages) MICROCHIP

159 / 320 page

 2001 Microchip Technology Inc.

Advance Information

DS39541A-page 159

PIC18C601/801

15.4

MSSP I2C Operation

The MSSP module in I2C mode, fully implements all

master and slave functions (including general call sup-

port) and provides interrupts on START and STOP bits

in hardware to determine a free bus (Multi-Master

mode). The MSSP module implements the standard

mode specifications, as well as 7-bit and 10-bit

addressing.

Two pins are used for data transfer. These are the RC3/

SCK/SCL pin, which is the clock (SCL), and the RC4/

SDI/SDA pin, which is the data (SDA). The user must

configure these pins as inputs or outputs through the

TRISC<4:3> bits.

The MSSP module functions are enabled by setting

MSSP Enable bit SSPEN (SSPCON1 register).

The MSSP module has these six registers for I2C oper-

ation:

• MSSP Control Register1 (SSPCON1)

• MSSP Control Register2 (SSPCON2)

• MSSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer (SSPBUF)

• MSSP Shift Register (SSPSR) - Not directly

accessible

• MSSP Address Register (SSPADD)

FIGURE 15-6:

MSSP BLOCK DIAGRAM

(I2C MODE)

The SSPCON1 register allows control of the I2C oper-

ation.

The

SSPM3:SSPM0

mode

selection

bits

(SSPCON1 register) allow one of the following I2C

modes to be selected:

• I2C Master mode, clock = OSC/(4*(SSPADD +1))

• I2C Slave mode (7-bit address)

• I2C Slave mode (10-bit address)

• I2C Slave mode (7-bit address), with START and

STOP bit interrupts enabled

• I2C Slave mode (10-bit address), with START and

STOP bit interrupts enabled

• I2C firmware controlled master operation, slave is

idle

Selection of any I2C mode with the SSPEN bit set,

forces the SCL and SDA pins to be open drain, pro-

vided these pins are programmed to inputs by setting

the appropriate TRISC bits.

15.4.1

SLAVE MODE

In Slave mode, the SCL and SDA pins must be config-

ured as inputs (TRISC<4:3> set). The MSSP module

will override the input state with the output data when

required (slave-transmitter).

When an address is matched, or the data transfer after

an address match is received, the hardware automati-

cally will generate the acknowledge (ACK) pulse and

load the SSPBUF register with the received value cur-

rently in the SSPSR register.

If either or both of the following conditions are true, the

MSSP module will not give this ACK pulse:

The buffer full bit BF (SSPCON1 register) was

set before the transfer was received.

The overflow bit SSPOV (SSPCON1 register)

was set before the transfer was received.

In this event, the SSPSR register value is not loaded

into the SSPBUF, but bit SSPIF (PIR registers) is set.

The BF bit is cleared by reading the SSPBUF register,

while bit SSPOV is cleared through software.

The SCL clock input must have a minimum high and

low for proper operation. The high and low times of the

I2C specification, as well as the requirement of the

MSSP module, is shown in timing parameter #100 and

parameter #101.

Read

Write

SSPSR reg

Match Detect

SSPADD reg

START and

STOP bit Detect

SSPBUF reg

Internal

Data Bus

Addr Match

Set, RESET

S, P bits

(SSPSTAT reg)

RC3/SCK/SCL

RC4/

Shift

Clock

MSb

SDI/

LSb

SDA

Note:

I/O pins have diode protection to VDD and VSS.

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