DM163006 datasheet(163/320 Pages) MICROCHIP

163 / 320 page

 2001 Microchip Technology Inc.

Advance Information

DS39541A-page 163

PIC18C601/801

15.4.3

MASTER MODE

Master mode of operation is supported by interrupt

generation on the detection of the START and STOP

conditions. The STOP (P) and START (S) bits are

cleared from a RESET, or when the MSSP module is

disabled. Control of the I2C bus may be taken when the

P bit is set, or the bus is idle, with both the S and P bits

clear.

In Master mode, the SCL and SDA lines are manipu-

lated by the MSSP hardware.

The following events will cause SSP Interrupt Flag bit,

SSPIF, to be set (SSP Interrupt if enabled):

• START condition

• STOP condition

• Data transfer byte transmitted/received

• Acknowledge Transmit

• Repeated START condition

15.4.4

I2C MASTER MODE SUPPORT

Master mode is enabled by setting and clearing the

appropriate SSPM bits in SSPCON1 and by setting the

SSPEN bit. Once Master mode is enabled, the user

has the following six options:

Assert a START condition on SDA and SCL.

Assert a Repeated START condition on SDA

and SCL.

Write to the SSPBUF register initiating transmis-

sion of data/address.

Generate a STOP condition on SDA and SCL.

Configure the I2C port to receive data.

Generate an Acknowledge condition at the end

of a received byte of data.

FIGURE 15-10:

MSSP BLOCK DIAGRAM (I

2C MASTER MODE)

Note:

The MSSP module, when configured in I2C

Master mode, does not allow queueing of

events. For instance, the user is not

allowed to initiate a START condition and

immediately write the SSPBUF register to

imitate transmission, before the START

condition is complete. In this case, the

SSPBUF will not be written to and the

WCOL bit will be set, indicating that a write

to the SSPBUF did not occur.

Read

Write

SSPSR

START bit, STOP bit,

SSPBUF

Internal

Data Bus

Set/Reset, S, P, WCOL (SSPSTAT)

Shift

Clock

MSb

LSb

SDA

Acknowledge

Generate

SCL

SCL In

Bus Collision

SDA In

SSPADD<6:0>

Baud

Set SSPIF, BCLIF

Reset ACKSTAT, PEN (SSPCON2)

Rate

Generator

SSPM3:SSPM0

Note:

I/O pins have diode protection to VDD and VSS.

START bit Detect

STOP bit Detect

Write Collision Detect

Clock Arbitration

State Counter for

End of XMIT/RCV

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