DM163006 datasheet(164/320 Pages) MICROCHIP

164 / 320 page

PIC18C601/801

DS39541A-page 164

Advance Information

 2001 Microchip Technology Inc.

15.4.4.1

I2C Master Mode Operation

The master device generates all of the serial clock

pulses and the START and STOP conditions. A trans-

fer is ended with a STOP condition or with a Repeated

START condition. Since the Repeated START condi-

tion is also the beginning of the next serial transfer, the

I2C bus will not be released.

In Master Transmitter mode, serial data is output

through SDA, while SCL outputs the serial clock. The

first byte transmitted contains the slave address of the

receiving device (7 bits) and the Read/Write (R/W) bit.

In this case, the R/W bit will be logic ’0’. Serial data is

transmitted eight bits at a time. After each byte is trans-

mitted, an Acknowledge bit is received. START and

STOP conditions are output to indicate the beginning

and the end of a serial transfer.

In Master Receive mode, the first byte transmitted con-

tains the slave address of the transmitting device

(7 bits) and the R/W bit. In this case, the R/W bit will be

logic ’1’. Thus, the first byte transmitted is a 7-bit slave

address followed by a ’1’ to indicate receive bit. Serial

data is received via SDA, while SCL outputs the serial

clock. Serial data is received eight bits at a time. After

each byte is received, an Acknowledge bit is transmit-

ted. START and STOP conditions indicate the begin-

ning and end of transmission.

The baud rate generator used for the SPI mode opera-

tion is now used to set the SCL clock frequency for

either 100 kHz, 400 kHz, or 1 MHz I2C operation. The

baud rate generator reload value is contained in the

lower 7 bits of the SSPADD register. The baud rate

generator will automatically begin counting on a write to

the SSPBUF. Once the given operation is complete

(i.e., transmission of the last data bit is followed by

ACK), the internal clock will automatically stop counting

and the SCL pin will remain in its last state.

A typical transmit sequence would go as follows:

The user generates a START condition by set-

ting the START enable (SEN) bit (SSPCON2

SSPIF is set. The MSSP module will wait the

required start time before any other operation

takes place.

The user loads the SSPBUF with the address to

transmit.

Address is shifted out the SDA pin until all eight

bits are transmitted.

The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

ACKSTAT bit (SSPCON2 register).

The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the SSPIF

bit.

The user loads the SSPBUF with eight bits of

data.

Data is shifted out the SDA pin until all eight bits

are transmitted.

The MSSP module shifts in the ACK bit from the

slave device and writes its value into the

ACKSTAT bit (SSPCON2 register).

The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the SSPIF

bit.

The user generates a STOP condition by setting

the STOP enable bit PEN (SSPCON2 register).

Interrupt is generated once the STOP condition

is complete.

15.4.5

BAUD RATE GENERATOR

In I2C Master mode, the reload value for the BRG is

located in the lower 7 bits of the SSPADD register

(Figure 15-11). When the BRG is loaded with this

value, the BRG counts down to 0 and stops until

another reload has taken place. The BRG count is dec-

remented twice per instruction cycle (TCY) on the Q2

and Q4 clocks. In I2C Master mode, the BRG is

reloaded automatically. If clock arbitration is taking

place, for instance, the BRG will be reloaded when the

SCL pin is sampled high (Figure 15-12).

FIGURE 15-11:

BAUD RATE GENERATOR BLOCK DIAGRAM

SSPM3:SSPM0

BRG Down Counter

CLKOUT

FOSC/4

SSPADD<6:0>

SSPM3:SSPM0

SCL

Reload

Control

Reload

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