DM163006 datasheet(165/320 Pages) MICROCHIP

165 / 320 page

 2001 Microchip Technology Inc.

Advance Information

DS39541A-page 165

PIC18C601/801

FIGURE 15-12:

BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

15.4.6

I2C MASTER MODE START

CONDITION TIMING

To initiate a START condition, the user sets the START

Condition Enable (SEN) bit (SSPCON2 register). If the

SDA and SCL pins are sampled high, the baud rate

generator

re-loaded

with

the

contents

SSPADD<6:0> and starts its count. If SCL and SDA are

both sampled high when the baud rate generator times

out (TBRG), the SDA pin is driven low. The action of the

SDA being driven low while SCL is high, is the START

condition, and causes the S bit (SSPSTAT register) to

be set. Following this, the baud rate generator is

reloaded with the contents of SSPADD<6:0> and

resumes its count. When the baud rate generator times

out (TBRG), the SEN bit (SSPCON2 register) will be

automatically cleared by hardware, the baud rate gen-

erator is suspended leaving the SDA line held low and

the START condition is complete.

15.4.6.1

WCOL Status Flag

If the user writes the SSPBUF when a START

sequence is in progress, the WCOL is set and the con-

tents of the buffer are unchanged (the write doesn’t

occur).

FIGURE 15-13:

FIRST START BIT TIMING

SDA

SCL

SCL de-asserted but slave holds

DX-1

BRG

SCL is sampled high, reload takes

place and BRG starts its count

03h

02h

01h

00h (hold off)

03h

02h

reload

BRG

value

SCL low (clock arbitration)

SCL allowed to transition high

BRG decrements on

Q2 and Q4 cycles

Note:

If at the beginning of the START condition,

the SDA and SCL pins are already sam-

pled low, or if during the START condition

the SCL line is sampled low before the

SDA line is driven low, a bus collision

occurs, the Bus Collision Interrupt Flag

BCLIF is set, the START condition is

aborted, and the I2C module is reset into its

IDLE state.

Note:

Because

queueing

events

not

allowed, writing to the lower 5 bits of

SSPCON2 is disabled until the START

condition is complete.

SDA

SCL

TBRG

1st bit

2nd bit

TBRG

SDA = 1,

At completion of START bit,

SCL = 1

Write to SSPBUF occurs here

TBRG

Hardware clears SEN bit

TBRG

Write to SEN bit occurs here

Set S bit (SSPSTAT)

and sets SSPIF bit

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