APL3518 datasheet(14/21 Pages) ANPEC

14 / 21 page

Rev. A.3 - Apr., 2011

APL3518/9

www.anpec.com.tw

Application Information

Input Capacitor

A 1

µF ceramic bypass capacitor from V

IN to GND, located

near the APL3518/9, is strongly recommended to sup-

press the ringing during short circuit fault event. Without

the bypass capacitor, the output short may cause suffi-

cient ringing on the input (from supply lead inductance) to

damage internal control circuitry.

Output Capacitor

A low-ESR 150

µF aluminum electrolytic or tantalum be-

tween V

OUT and GND is strongly recommended to reduce

the voltage drop during hot-attachment of downstream

peripheral. (Per USB 2.0, output ports must have a mini-

mum 120

µF of low-ESR bulk capacitance per hub).

Higher-value output capacitor is better when the output

load is heavy. Additionally, bypassing the output with a

0.1

µF ceramic capacitor improves the immunity of the de-

vice to short-circuit transients.

Layout Consideration

The PCB layout should be carefully performed to maxi-

mize thermal dissipation and to minimize voltage drop,

droop and EMI. The following guidelines must be

considered:

1. Please place the input capacitors near the VIN pin as

close as possible.

2. Output decoupling capacitors for load must be placed

near the load as close as possible for decoupling high-

frequency ripples.

3. Locate APL3518/9 and output capacitors near the load

to reduce parasitic resistance and inductance for ex-

cellent load transient performance.

4. The negative pins of the input and output capacitors

and the GND pin must be connected to the ground plane

of the load.

5. Keep V

IN and VOUT traces as wide and short as possible.

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