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APW8811 Datasheet(PDF) 13 Page - Anpec Electronics Coropration

Part # APW8811
Description  System Power PWM Controller for Notebook Computers
PDF  23 Pages
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Manufacturer  ANPEC [Anpec Electronics Coropration]
Direct Link  http://www.anpec.com.tw
Logo ANPEC - Anpec Electronics Coropration

APW8811 Datasheet(HTML) 13 Page - Anpec Electronics Coropration

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Copyright
© ANPEC Electronics Corp.
Rev. A.3 - Sep., 2012
APW8811
www.anpec.com.tw
13
Under-Voltage Protection (PWMs)
In the process of operation, if a short-circuit occurs, the
output voltage will drop quickly. When load current is big-
ger than the value of current-limit threshold, the output
voltage will fall out of the required regulation range. The
under-voltage continually monitors the setting output volt-
age after soft-start is completed. If a load step is strong
enough to pull the output voltage lower than the under-
voltage threshold for at least 2
µs, the PWM controller starts
a soft-stop process to shut down the output gradually. As
long as either of PWM channels triggers under-voltage,
both of PWM channels active under-voltage protection
and latched off when the soft-stop process is completed.
The under-voltage threshold is 70% of the nominal out-
put voltage. Under-voltage protection is ignored for at least
2ms(typ.) after a rising edge on EN. Toggling ENLDO or
ENPWM signal will clear the latch and bring the chip back
to operation.
Function Description (Cont.)
POK is actively held low in shutdown, standby, and soft-
start. In the soft-start process, the POK is an open-drain
output, and it is released with enable delay after ENPWM
goes high (about 2ms typ.). In normal operation, the POK
window is from 90% to its OVP threshold of the converter
reference voltage. Both of V
OUT1 and VOUT2 have to stay
within this window for POK to be high (AND gated). In
order to prevent false POK drop, capacitors need to par-
allel at the output to confine the voltage deviation with
severe load step transient.
Power Good Indicator (PWMs)
Should the output voltage of V
OUT1 and VOUT2 increase over
25% of the setting voltage due to the high-side MOSFET
failure or for other reasons, the over-voltage protection
will active. As long as either of PWM channels triggers
over-voltage, both of PWM channels active overvoltage
protection. Over-voltage protection will force the low-side
MOSFET gate driver fully turn on. This action actively pulls
down the output voltage. When the OVP occurs, the POK
pin will pull down and latch-off the converter. This OVP
scheme only clamps the voltage overshoot, and does not
invert the output voltage when otherwise activated with a
Over-Voltage Protection (OVP)
When the junction temperature increases above the ris-
ing threshold temperature 160°C, the IC will enter the
over -temperature protection (OTP). When the OTP occurs,
REF, LDO and PWM controllers circuitry shuts down. It is
non-latch protection.
Over-Temperature Protection
The current-limit circuit employs a “valley” current-sens-
ing algorithm (See Figure 1). The APW8811 uses the low-
side MOSFET’s R
DS(ON) of the synchronous rectifier as a
current-sensing element. If the magnitude of the current-
sense signal at PHASE pin is above the current-limit
threshold, the PWM is not allowed to initiate a new cycle.
The actual peak current is greater than the current-limit
threshold by an amount equal to the inductor ripple
current. Therefore, the exact current-limit characteristic
and maximum load capability are a function of the sense
resistance, inductor value, and input voltage.
Current-Limit (PWMs)
Both PWM controllers use the low-side MOSFETs on-
resistance R
DS(ON) to monitor the current for protection
against shorted outputs. The MOSFET’s R
DS(ON)
is varied
by temperature and gate to source voltage, the user
should determine the maximum R
DS(ON)
in manufacture’s
datasheet.
The current-Limit threshold of APW8811 is adjusted with
continuously high output from low-side MOSFET driver.
It’s a common problem for OVP schemes with a latch.
Once an over-voltage fault condition is set, it can be reset
by toggling ENLDO or ENPWM signal.
Time
0
I
PEAK
I
OUT
I
LIMIT
∆I
Figure 1. Current-Limit Algorithm



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