Copyright

© ANPEC Electronics Corp.

Rev. A.4 - Jan., 2013

www.anpec.com.tw

14

APA3160

Function Description (Cont.)

Right-Justified

Right-justified (RJ) timing uses LRCLK to define the data for the left channel and the right channel when the data

being transmitted. For the left channel, the LRCLK is high; for the right channel, the LRCLK low. A bit clock running at

32, 48, or 64 × f

8 bit-clock. In RJ mode, the LSB of data is always clocked by the last bit clock before LRCLK transitions. The data is

written MSB first and is valid on the rising edge of bit clock. The DAP masks unused leading data bit positions.

Figure 7. Right-Justified 64 f

Figure 8. Right-Justified 48 f

Figure 9. Right-Justified 32 f

23 22

19 18

15 14

1

0

19 18

15 14

1

0

15 14

1

0

32 Clks

32 Clks

LRCLK

Left Channel

Right Channel

SCLK

SCLK

MSB

MSB

LSB

LSB

24-Bit Mode

20-Bit

Mode

16-Bit

Mode

23 22

19 18

15 14

1

0

19 18

15 14

1

0

15

14

1

0

24-Bit Mode

20-Bit

Mode

16-Bit

Mode

23 22

19 18

15 14

1

0

19

18

15 14

1

0

1

0

24 Clks

24 Clks

LRCLK

Left Channel

Right Channel

SCLK

SCLK

MSB

MSB

LS

B

LS

B

24-Bit Mode

20-Bit

Mode

16-Bit

Mode

24-Bit Mode

6

5

2

6

5

2

15 14

6

5

2

23 22

19 18

15 14

1

0

19 18

15 14

1

0

1

0

20-Bit

Mode

16-Bit

Mode

6

5

2

6

5

2

15 14

6

5

2

15 14

12 11

9

8

5

4

16 Clks

16Clks

LRCLK

Left Channel

Right Channel

SCLK

SCLK

MSB

LSB

LSB

16-Bit Mode

3

2

1

0

MSB

16-Bit Mode

13

10

15 14

12 11

9

8

5

4

3

2

1

13

10

0