AD5280 datasheet(4/28 Pages) AD

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AD5280/AD5282

Rev. C | Page 4 of

Parameter

Symbol

Conditions

Min

Typ1

Max

Unit

Total Harmonic Distortion

THDW

VA = 1 V rms, RAB = 20 kΩ

0.014

VB = 0 V dc, f = 1 kHz

VW Settling Time

VA = 5 V, VB = 5 V, ±1 LSB error band

μs

Crosstalk

VA = VDD, VB = 0 V, measure VW1 with

adjacent RDAC making full-scale

code change

nV-s

Analog Crosstalk

CTA

Measure VW1 with VW2 = 5 V p-p @ f =

10 kHz

−62

Resistor Noise Voltage

eN_WB

RWB = 20 kΩ, f = 1 kHz

nV/√Hz

INTERFACE TIMING CHARACTERISTICS (applies to all parts)6, 10, 11

SCL Clock Frequency

fSCL

400

kHz

tBUF Bus Free Time Between

Stop and Start

1.3

μs

tHD:STA Hold Time (Repeated

Start)

After this period, the first clock pulse

is generated

0.6

μs

tLOW Low Period of SCL Clock

1.3

μs

tHIGH High Period of SCL Clock

0.6

μs

tSU:STA Setup Time for Start

Condition

0.6

μs

tHD:DAT Data Hold Time

0.9

μs

tSU:DAT Data Setup Time

100

tF Fall Time of Both SDA and

SCL Signals

300

tR Rise Time of Both SDA and

SCL Signals

300

tSU:STO Setup Time for STOP

Condition

t10

0.6

μs

1 Typicals represent average readings at 25°C, VDD = +5 V, VSS = −5 V.

2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3 VAB = VDD, wiper (VW) = no connect.

4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits

of ±1 LSB maximum are guaranteed monotonic operating conditions.

5 Resistor Terminal A, Resistor Terminal B, and Wiper Terminal W have no limitations on polarity with respect to each other.

6 Guaranteed by design and not subject to production test.

7 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

8 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest

bandwidth. The highest R value results in the minimum overall power consumption.

9 All dynamic characteristics use VDD = 5 V.

10 See timing diagram (Figure 3) for location of measured values.

11 Standard I2C mode operation is guaranteed by design.

t10

SCL

SDA

Figure 3. Detailed Timing Diagram

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