AD5280 datasheet(18/28 Pages) AD

18 / 28 page

AD5280/AD5282

Rev. C | Page 18 of

LEVEL SHIFT FOR BIDIRECTIONAL INTERFACE

While most old systems can be operated at one voltage, a new

component can be optimized at another. When two systems

operate the same signal at two different voltages, proper level

shifting is needed. For instance, a 3.3 V EEPROM can interface

with a 5 V digital potentiometer. A level-shift scheme is needed

to enable a bidirectional communication so that the setting of

the digital potentiometer can be stored to and retrieved from

the EEPROM. Figure 49 shows one of the implementations.

M1 and M2 can be any N-channel signal FETs or low threshold

FDV301N if VDD falls below 2.5 V.

AD5282

SCL2

SDA2

SCL1

SDA1

3.3V

EEPROM

VDD1 = 3.3V

VDD2 = 5V

LEVEL SHIFTED

Figure 49. Level Shift for Different Potential Operation

LEVEL SHIFT FOR NEGATIVE VOLTAGE

OPERATION

The digital potentiometer is popular in laser diode driver

applications and certain telecommunications equipment level-

setting applications. These applications are sometimes

operated between ground and a negative supply voltage such

that the systems can be biased at ground to avoid large bypass

capacitors that may significantly impede the ac performance.

Like most digital potentiometers, the AD5280/AD5282 can be

configured with a negative supply (see Figure 50).

–5V

LEVEL SHIFTED

VDD

VSS

GND

SDA

SCL

Figure 50. Biased at Negative Voltage

However, the digital inputs must also be level shifted to allow

proper operation because the ground is referenced to the

negative potential. Figure 51 shows one implementation with a

few transistors and a few resistors. When VIN is below the Q3

threshold value, Q3 is off, Q1 is off, and Q2 is on. In this state,

VOUT approaches 0 V. When VIN is above 2 V, Q3 is on, Q1 is on,

and Q2 is turned off. In this state, VOUT is pulled down to VSS.

Be aware that proper time shifting is also needed for successful

communication with the device.

+5V

10kΩ

VSS = –5V

VOUT

–5V

VIN

Figure 51. Level Shift for Bipolar Potential Operation

ESD PROTECTION

All digital inputs are protected with a series input resistor and

parallel Zener ESD structures, as shown in Figure 52. The

protection applies to digital inputs SDA, SCL, and SHDN.

LOGIC

340Ω

VSS

Figure 52. ESD Protection of Digital Pins

TERMINAL VOLTAGE OPERATING RANGE

The AD5280/AD5282 positive VDD and negative VSS power

supply defines the boundary conditions for proper 3-terminal

digital potentiometer operation. Supply signals present on

Resistor Terminal A, Resistor Terminal B, and Wiper Terminal

W that exceed VDD or VSS are clamped by the internal forward-

biased diodes (see Figure 53).

VDD

VSS

Figure 53. Maximum Terminal Voltages Set by VDD and VSS

POWER-UP SEQUENCE

Because there are ESD protection diodes that limit the voltage

compliance at Terminal A, Terminal B, and Terminal W (see

Figure 53), it is important to power VDD/VSS before applying any

voltage to the A, B, and W terminals. Otherwise, the diode is

forward biased such that VDD/VSS is unintentionally powered,

which may affect the rest of the user’s circuit. The ideal power-

up sequence is the following: GND, VDD, VSS, digital inputs, and

VA/VB/VW. The order of powering VA/VB/VW and digital inputs

is not important as long as they are powered after VDD/VSS.

AD5280 Datasheet(PDF) 18 Page - Analog Devices

AD5280 Datasheet(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL