AD5280/AD5282

Rev. C | Page 15 of

28

input voltage applied to Terminal A and Terminal B is

()

B

A

W

V

V

D

V

256

256

+

=

D

D

256 −

()

()

(3)

For a more accurate calculation that includes the effect of wiper

()

B

AB

WA

A

AB

WB

W

V

R

D

R

V

R

D

R

D

V

+

=

(4)

Operation of the digital potentiometer in divider mode results

in a more accurate operation over temperature. Unlike rheostat

mode, the output voltage is dependent mainly on the ratio of

values; therefore, the temperature drift reduces to 5 ppm/°C.

19

1

1

99

SCL

SDA

START BY

MASTER

FRAME 1

SLAVE ADDRESS BYTE

ACK. BY

AD5280/5282

FRAME 2

INSTRUCTION BYTE

ACK. BY

AD5280/AD5282

FRAME 3

DATA BYTE

ACK. BY

AD5280/5282

STOP BY

MASTER

01

0

11 AD1

R/W

A/B

RS

SD

O1

O2

X

X

X

D7

D6D5D4D3D2D1D0

AD0

Figure 45. Writing to the RDAC Register

1

91

9

SCL

SDA

ACK. BY

AD5280/AD5282

NO ACK. BY

MASTER

START BY

MASTER

FRAME 1

SLAVE ADDRESS BYTE

FRAME 2

DATA BYTE FROM PREVIOUSLY SELECTED

STOP BY

MASTER

0

1

0

1

1

AD1 AD0 R/W

D7D6D5D4D3D2

D1D0

A

Figure 46. Reading Data from a Previously Selected RDAC Register in Write Mode

S

0

1

0

1

1

AD1

AD

0

R/

W

A

A/B

RS

S

D

X X

X

A

D7

D6

D

5

D

4

D

3

D

2

D

1

D

0

A

P

Slave Address Byte

Instruction Byte

Data Byte

where:

Abbreviation

Equals

S

Start condition

P

Stop condition

A

Acknowledge

X

Don’t care

AD1, AD0

Package pin programmable address bits

R/W

Read enable at high and write enable at low

A/B

RDAC subaddress select; 0 = RDAC1 and 1 = RDAC2

RS

Midscale reset, active high (only affects selected channel)

SD

Shutdown; same as SHDN pin operation except inverse logic (only affects selected channel)

O , O

2

1

Output logic pin latched values; default Logic 0

D7, D6, D5, D4, D3, D2, D1, D0

Data bits