REV. 0

–18–

AD7738

Mode Register

8 Bits Read/Write Register, Address 38h–3Fh, Default Value 00h

The Mode register configures the part and determines the part’s operating mode. Writing to the Mode register will clear the ADC

Status register, set the

RDY pin to logic high level, exit all current operations, and start the mode specified by the Mode bits.

The AD7738 contains only one Mode register. The three LSBs of the address used for writing to the Mode register specify the channel

selected for operation determined by the MD2 to MD0 bits. The address 38h only must be used for reading from the Mode register.

Bit

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Mnemonic

MD2

MD1

MD0

CLKDIS

DUMP

CONT RD

24/16 BIT

CLAMP

Default

0

0

0

0

0

0

0

0

Bit

Mnemonic

Description

7–5

MD2–MD0

Mode Bits. These three bits determine the AD7738 operation mode. Writing a new value to the Mode

bits will exit the part from the mode in which it has been operating and place it in the new requested

mode immediately. The function of the Mode bits is described in more detail below.

4

CLKDIS

Master Clock Output Disable. When this bit is set to 1 the master clock is disabled from appearing

at the MCLKOUT pin and the MCLKOUT pin is in a high impedance state. This allows turning off the

MCLKOUT as a power saving feature. When using an external clock on MCLKIN, the AD7738

continues to have internal clocks and will convert normally regardless of CLKDIS bit state. When using

a crystal oscillator or ceramic resonator across the MCLKIN and MCLKOUT pins, the AD7738 clock is

stopped and no conversions can take place when the CLKDIS bit is active. The AD7738 digital interface

can still be accessed using the SCLK pin.

3

DUMP

DUMP Mode. When this bit is reset to 0, the Channel Status register and Channel Data register will

be addressed and read separately. When the DUMP bit is set to 1, the Channel Status register will be followed

immediately by a read of the Channel Data register regardless of whether the Status or Data register

has been addressed through the Communication register. The Continuous Read mode will always be a

“Dump Mode” reading of the Channel Status and Data register regardless of the Dump Bit value. See the

Digital Interface Description section for more details.

2

CONT RD

When this bit is set to 1, the AD7738 will operate in the Continuous Read mode. See the Digital

Interface Description section for more details.

1

24/16 BIT

The Channel Data Register Data Width Selection Bit. When set to 1, the Channel Data registers will be

24 bits wide. When set to 0, then the Channel Data registers will be 16 bits wide.

0

CLAMP

This bit determines the Channel Data register’s value when the analog input voltage is outside the nominal

input voltage range. When the CLAMP bit is set to 1, the Channel Data register will be digitally clamped

either to all zeros or all ones when the analog input voltage goes outside the nominal input voltage range.

When the CLAMP bit is reset to 0, the Data registers reflect the analog input voltage even outside the

nominal voltage range. See the Analog Inputs Extended Voltage Range section.

MD2

MD1

MD0

Mode

Address Used for Mode Register Write Specify

000

Idle Mode

001Continuous Conversion Mode

The First Channel to Start Converting

010

Single Conversion Mode

Channel to Convert

011Power Down (Standby) Mode

100

ADC Zero-Scale Self Calibration

Channel Conversion Time Used for the ADC Self-Calibration

101For Future Use

110Channel Zero-Scale System Calibration

Channel to Calibrate

111Channel Full-Scale System Calibration

Channel to Calibrate