AD7738 datasheet(23/28 Pages) AD

23 / 28 page

REV. 0

AD7738

–23–

DIN

48h

00h

DATA

00h

DATA

00h

CH.STAT.

READ CH0

DATA REGISTER

READ

CH0

STATUS

48h

WRITE

COMM.

SCLK

DOUT

WRITE

COMM.

WRITE

MODE

RDY

38h

00h

DATA

00h

DATA

00h

CH.STAT.

READ CH1 DATA

READ

CH1

STATUS

CONVERSION

ON CH0

COMPLETE

CONVERSION

ON CH1

COMPLETE

Figure 12. Continuous Conversion CH0 and CH1, Continuous Read

Continuous Read (Continuous Conversion) Mode

When the Continuous RD bit in the Mode register is set, the

first write “48h” to the communication register starts the Continu-

ous Read mode. As shown in Figure 12, subsequent accesses

to the part sequentially reads the Channel Status and Data

registers of the last completed conversion without any further

configuration of the Communication register being required.

Note that the Continuous Conversion bit in the Mode register

should be set when entering the Continuous Read mode.

Note that the Continuous Read mode is “Dump Mode” reading

of the Channel Status and Data register regardless of the Dump

bit value. Use the Channel bits in the Channel Status register to

check/recognize which channel data is actually being shifted out.

Note that the last completed conversion result is being read.

Therefore, the RDYFN bit in the I/O Port register should be 0,

and reading the result should always start before the next con-

version is completed.

The AD7738 will stay in Continuous Read mode as long as the

DIN pin is low while the

CS pin is low. Therefore, write 0 to

the AD7738 while reading in Continuous Read mode. To

exit Continuous Read mode, take the DIN pin high for at least

100 ns after a read is complete. (Write “80h” to the AD7738 to

exit continuous reading.)

The Continuous RD bit in the Mode register is not changed

by taking the DIN pin high. Therefore, the next write “48h”

starts the Continuous Read mode again. To completely stop

the continuous read mode, write to the Mode register to clear

the Continuous RD bit.

CIRCUIT DESCRIPTION

The AD7738 is a sigma-delta A/D converter, intended for the

measurement of wide dynamic range, low frequency signals in

industrial process control, instrumentation, PLC, and DSC.

It contains a multiplexer, an input buffer, a sigma-delta (or

charge-balancing) ADC, digital filter, clock oscillator, digital I/O

port, and a serial communications interface.

Analog Front End

The AD7738 has nine analog input pins connected to the

ADC through the internal multiplexer. The analog front end

can be configured as eight single-ended inputs four differen-

tial inputs, or any combination of these. Selection of ADC

inputs is determined via the COM0 and COM1 bits in

the Channel Setup registers.

The AD7738 contains a wide bandwidth, fast settling time

differential input buffer capable of driving the dynamic load of a

high speed sigma-delta modulator. With the internal buffer

enabled, the analog inputs feature relatively high input imped-

ance. However, if chopping is enabled and/or when switching

between channels, there is a dynamic current charging the

capacitance of the multiplexer, capacitance of the pins, and any

additional capacitance connected to the MUXOUT. In typical

configurations with MUXOUT connected directly to the

ADCIN, this capacitance could be approximately 20 pF. The

AD7738 has been designed to provide adequate settling time

after a multiplexer switch and before the actual sampling starts

only if the analog inputs resistive source impedance does not

exceed 10 k

Ω.

An RC connected to the analog inputs may convert the dynamic

charging currents to a dc voltage and cause additional gain or

offset errors. The recommended low-pass RC filter on the

AD7738 analog inputs is 20

Ω and 100 nF.

The multiplexer output and the ADC input are pinned out

externally. This facilitates shared signal conditioning between

the multiplexer and the ADC. Please note that if chop is enabled

and/or when switching between channels, any circuit connected

between MUXOUT and ADCIN should be fully settled within

the settling time provided by the AD7738. See the Multiplexer,

Conversion, and Data Output Timing section.

ADC

The AD7738 core consists of a charge balancing sigma-delta

modulator and a digital filter. The architecture is optimized for

fast fully settled conversion. This allows for fast channel-to-channel

switching while maintaining inherently excellent linearity, high

resolution, and low noise.

Chopping

With chopping enabled, the multiplexer repeatedly reverses the

ADC inputs. Every output data result is then calculated as an

average of two conversions, the first with positive and the sec-

ond with negative offset term included. This effectively removes

any offset error of the input buffer and sigma-delta modulator,

resulting in excellent dc offset and offset drift specifications.

Figure 13 shows the channel signal chain with chopping enabled.

AD7738 Datasheet(PDF) 23 Page - Analog Devices

AD7738 Datasheet(HTML) 23 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL