Version 0.1

SFH 7776

2013-07-09

27

DRAFT - For reference only.

Subject to change without notice.

ALS_VIS_TL_LSBs register (0x51h)

LSB for the ALS VIS threshold „LOW“.

ALS_VIS_TL_MSBs register (0x52h)

MSB for the ALS VIS threshold „LOW“.

INT modes

The Interrupt function compares ALS and PS measurement values with the current interrupt threshold

level. PS and ALS VIS Interrupt status is readable via register 0x4Ah or at the INT pin of the sensor.

The Interrupt persistence function is only valid for PS measurements and is defined at register (0x43h).

The INT pin of the SFH 7776 is an open drain output and should be pulled-up to V

resistor. When VDD is supplied to the sensor the INT pin is per default in high ohmic (inactive) state.

The INT status becomes inactive by writing an INT reset command, reading the INT status register or

performing a software reset.

The INT status stays in its last state when the sensor is set to the standby mode. In the INT active state

„low“ the sensor consumes ~25µA extrra current. Therefore OSRAM recommends to set the INT state

to high impedance before setting the sensor in standby mode.

Below the ALS and PS INT modes are described for the unlatched mode. In latched mode the switching

back to the „inactive“ INT state is depending on an interrupt reset or on reading out the INT status reg-

ister.

ALS INT mode:

The ALS VIS threshold levels high (register 0x4Fh & 0x50h) and low (register 0x4Fh & 0x50h)

are only valid for the ALS VIS measurement values. The ALS VIS INT mode is fixed and can not

be adapted via register. The thresholds define a window with the following functionality:

ALS INT is active, if the ALS VIS measurement values are outside the window

ALS INT is inactive, if the ALS VIS measurement results are inside the window.

PS INT Modes: Bit <5;4> of interrupt function setting register (0x4Ah)

00 PS_TH is active only:

The INT state is active, if the PS measurement result is equal or higher than the set PS_TH high

threshold.

R/W-Register 0x51

Bit

7

6

5

4

3

2

1

0

2

7

2

6

2

5

2

4

2

3

2

2

2

1

2

0

default

000

000

00

R/W-Register 0x52

Bit

7

6

5

4

3

2

1

0

2

15

2

14

2

13

2

12

2

11

2

10

2

9

2

8

default

000

000

00