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APA300 Datasheet(PDF) 29 Page - Actel Corporation |
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APA300 Datasheet(HTML) 29 Page - Actel Corporation |
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29 / 174 page  ProASICPLUS Flash Family FPGAs v5.2 1-25 Note: Each RAM block contains a multiplexer (called DMUX) for each output signal, increasing design efficiency. These DMUX cells do not consume any core logic tiles and connect directly to high-speed routing resources between the RAM blocks. They are used when RAM blocks are cascaded and are automatically inserted by the software tools. Figure 1-22 • Basic FIFO Block Diagrams Table 1-14 • Memory Block FIFO Interface Signals FIFO Signal Bits In/Out Description WCLKS 1 In Write clock used for synchronization on write side RCLKS 1 In Read clock used for synchronization on read side LEVEL <0:7> 8 In Direct configuration implements static flag logic RBLKB 1 In Read block select (active Low) RDB 1 In Read pulse (active Low) RESET 1 In Reset for FIFO pointers (active Low) WBLKB 1 In Write block select (active Low) DI<0:8> 9 In Input data bits <0:8>, <8> will be generated parity if PARGEN is true WRB 1 In Write pulse (active Low) FULL, EMPTY 2 Out FIFO flags. FULL prevents write and EMPTY prevents read EQTH, GEQTH 2 Out EQTH is true when the FIFO holds the number of words specified by the LEVEL signal. GEQTH is true when the FIFO holds (LEVEL) words or more DO<0:8> 9 Out Output data bits <0:8>. <8> will be parity output if PARGEN is true. RPE 1 Out Read parity error (active High) WPE 1 Out Write parity error (active High) LGDEP <0:2> 3 In Configures DEPTH of the FIFO to 2 (LGDEP+1) PARODD 1 In Parity generation/detect – Even when Low, Odd when High FIFO (256x9) LEVEL<0:7> DO <0:8> DI<0:8> WRB RDB WBLKB RBLKB RPE PARODD WPE LGDEP<0:2> FULL EMPTY EQTH GEQTH WCLKS RCLKS RESET RESET RPE WPE FULL EMPTY EQTH GEQTH DO <0:8> RPE WPE FULL EMPTY EQTH GEQTH DI <0:8> DO <0:8> LEVEL <0:7> WRB RDB WBLKB RBLKB RPE PARODD WPE LGDEP<0:2> DI <0:8> LEVEL <0:7> WRB RDB WBLKB RBLKB PARODD LGDEP<0:2> FULL EMPTY EQTH GEQTH RCLKS RESET RESET LEVEL<0:7> DI<0:8> WRB RDB WBLKB RBLKB PARODD LGDEP<0:2> WCLKS DO <0:8> FIFO (256x9) FIFO (256x9) FIFO (256x9) Sync Write and Sync Read Ports Sync Write and Async Read Ports Async Write and Sync Read Ports Async Write and Async Read Ports |
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