APA300 datasheet(55/174 Pages) ACTEL

55 / 174 page

ProASICPLUS Flash Family FPGAs

v5.2

1-51

Module Delays

Sample Macrocell Library Listing

Figure 1-29 • Module Delays

Table 1-45 • Worst-Case Military Conditions1

VDD = 2.3 V, TJ = 70º C, TJ = 70°C, TJ = 125°C for Military/MIL-STD-883

Cell Name

Description

Std.

–F2

Max

Min

Max

Min

Units

NAND2

2-Input NAND

0.5

0.6

AND2

2-Input AND

0.7

0.8

NOR3

3-Input NOR

0.8

1.0

MUX2L

2-1 MUX with Active Low Select

0.5

0.6

OA21

2-Input OR into a 2-Input AND

0.8

1.0

XOR2

2-Input Exclusive OR

0.6

0.8

LDL

Active Low Latch (LH/HL)

LH3

0.9

1.1

CLK-Q

HL3

0.8

0.9

tsetup

0.7

0.8

thold

0.1

0.2

DFFL

Negative Edge-Triggered D-type Flip-Flop (LH/HL)

CLK-Q

LH3

0.9

1.1

HL3

0.8

1.0

tsetup

0.6

0.7

thold

0.0

Notes:

1. Intrinsic delays have a variable component, coupled to the input slope of the signal. These numbers assume an input slope typical of

local interconnect.

2. All –F parts are only available as commercial.

3. LH and HL refer to the Q transitions from Low to High and High to Low, respectively.

50%

50% 50%

50%

DALH

50%50%

50%

DBLH

DAHL

DBHL

DCHL

DCLH

50%

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