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APA300 Datasheet(PDF) 63 Page - Actel Corporation |
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APA300 Datasheet(HTML) 63 Page - Actel Corporation |
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63 / 174 page  ProASICPLUS Flash Family FPGAs v5.2 1-59 Asynchronous SRAM Read, RDB Controlled Note: The plot shows the normal operation status. Figure 1-35 • Asynchronous SRAM Read, RDB Controlled Table 1-54 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units Notes ORDA New DO access from RB ↓ 7.5 ns ORDH Old DO valid from RB ↓ 3.0 ns RDCYC Read cycle time 7.5 ns RDMH RB high phase 3.0 ns Inactive setup to new cycle RDML RB low phase 3.0 ns Active RPRDA New RPE access from RB ↓ 9.5 ns RPRDH Old RPE valid from RB ↓ 3.0 ns Note: All –F speed grade devices are 20% slower than the standard numbers. RB=(RDB+RBLKB) RPE DO tORDH tORDA tRPRDA tRDML tRDCYC tRDMH tRPRDH |
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