5910

HIGH-VOLTAGE BiMOS III

10-BIT SERIAL-INPUT,

LATCHED DRIVERS

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

TRUTH TABLE

Serial

Shift Register Contents

Serial

Latch Contents

Output Contents

Data Clock

Data

Strobe

Output Input

HH

LL

XXX...

X

X

X

L

X

X

X

...

X

X

H

L

L

L

... L

L

L = Low Logic Level

H = High Logic Level

X = Irrelevant

P = Present State

R = Previous State

Serial Data present at the input is transferred

to the shift register on the logic “0” to logic “1”

transition of the CLOCK input pulse. On

succeeding CLOCK pulses, the registers shift data

information towards the SERIAL DATA OUT-

PUT. The SERIAL DATA must appear at the

input prior to the rising edge of the CLOCK input

waveform.

Information present at any register is trans-

ferred to the respective latch when the STROBE

is high (serial-to-parallel conversion). The

latches will continue to accept new data as long as

the STROBE is held high. Applications where

the latches are bypassed (STROBE tied high) will

require that the BLANKING input be high during

serial data entry.

When the BLANKING input is high, the

output source drivers are disabled (OFF); the

DMOS sink drivers are ON. The information

stored in the latches is not affected by the

BLANKING input. With the BLANKING input

low, the outputs are controlled by the state of

their respective latches.

TIMING CONDITIONS

A. Minimum Data Active Time Before Clock Pulse

(Data Set-Up Time) ...........................................................................

75 ns

B. Minimum Data Active Time After Clock Pulse

(Data Hold Time) ...............................................................................

75 ns

C. Minimum Data Pulse Width ............................................................. 150 ns

D. Minimum Clock Pulse Width ........................................................... 100 ns

E. Minimum Time Between Clock Activation and Strobe .................... 300 ns

F. Minimum Strobe Pulse Width .......................................................... 100 ns

G. Typical Time Between Strobe Activation and

Output Transition .............................................................................

750 ns

E

F

CLOCK

DATA IN

STROBE

BLANKING

A

D

B

C

G

Dwg. No. A-12,649A