MP1469 – SYNCHRONOUS, STEP-DOWN CONVERTER WITH INTERNAL MOSFETS

MP1469 Rev. 1.01

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13

8/26/2013

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capacitors to limit the output voltage ripple.

Estimate the output voltage ripple with:

OUT

OUT

OUT

ESR

S1

IN

S

VV

1

V1

R

fL

V

8 f

C2

⎛⎞

⎛⎞

Δ=

× −

×

+

⎜⎟

⎜⎟

×× ×

⎝⎠ ⎝⎠

equivalent series resistance (ESR) of the output

capacitor.

For

ceramic

capacitors,

the

capacitance

dominates the impedance at the switching

frequency and causes most of the output

voltage ripple. For simplification, estimate the

output voltage ripple with:

OUT

OUT

OUT

2

IN

S1

VV

ΔV1

V

8f

L

C2

⎛⎞

=× −

⎜⎟

×× ×

⎝⎠

For tantalum or electrolytic capacitors, the ESR

dominates the impedance at the switching

frequency. For simplification, the output ripple

can be approximated with:

OUT

OUT

OUT

ESR

IN

S1

VV

ΔV1

R

fL

V

⎛⎞

=× −

×

⎜⎟

×

⎝⎠

The characteristics of the output capacitor also

affect the stability of the regulation system. The

MP1469 can be optimized for a wide range of

capacitance and ESR values.

External Bootstrap Diode

An external bootstrap (BST) diode can enhance

the efficiency of the regulator givien the

following applicable conditions:

Duty cycle is high: D=

IN

OUT

V

V

>65%

Connect the external BST diode from the output

of voltage regulator to the BST pin, as shown in

Figure 7.

MP1469

SW

L

5V or 3.3V

R4

External BST Diode

IN4148

BST

Figure 7: Optional External Bootstrap Diode

For most applications, use an IN4148 for the

external BST diode is IN4148, and a 1µF

capacitor for the BST cap.

PC Board Layout

PCB layout is very important to achieve stable

operation. For best results, use the following

guidelines and Figure 8 as reference.

1) Keep the connection between the input

ground and GND pin as short and wide as

possible.

2) Keep the connection between the input

capacitor and IN pin as short and wide as

possible.

3) Use short and direct feedback connections.

Place the feedback resistors and compensation

components as close to the chip as possible.

4) Route SW away from sensitive analog areas

such as FB.

C1

C1A

C2

C2A

L1

R1

R2

R7

C3

R6

C5

R4

R5

12

3

4

5

6

GND

R3

3

C4

SW