MP3900DS datasheet(10/13 Pages) MPS

10 / 13 page

MP3900 – HIGH EFFICIENCY BOOST CONTROLLER

MP3900 Rev. 1.0

www.MonolithicPower.com

12/17/2013

MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.

Boost Converter: Compensation Design

The output of the transconductance error

amplifier (COMP) is used to compensate the

regulation control system. The system uses two

poles and one zero to stabilize the control loop.

The poles are fP1, which is set by the output

capacitor (C2) and load resistance and fP2,

which starts from origin. The zero (fZ1) is set by

the compensation capacitor (C3) and the

compensation resistor (R3). These parameters

are determined by the equations:

LOAD

f 1

Where RLOAD is the load resistance.

The DC mid-band loop gain is:

SENSE

OUT

REF

LOAD

VDC

where VREF is the voltage reference, 0.8V. AET is

the gain of error amplifier translator and GEA is

the error amplifier transconductance.

The ESR zero in this example locates at very

high frequency. Therefore, it is not taken into

design consideration.

There is also a right-half-plane zero (fRHPZ) that

exists in continuous conduction mode (inductor

current does not drop to zero on each cycle)

step-up converters. The frequency of the right

half plane zero is:

OUT

LOAD

RHPZ

The right-half-plane zero increases the gain and

reduces the phase simultaneously, which

results in smaller phase margin and gain

margin. The worst case happens at the

condition of minimum input voltage and

maximum output power.

In order to achieve system stability, fz1 is placed

close to fP1 to cancel the pole. R3 is adjusted to

change the voltage gain. Make sure the

bandwidth is about 1/10 of the lower one of the

ESR zero and the right-half-plane zero.

LOAD

REF

SENSE

OUT

Based on these equations, R3 and C3 can be

solved.

For the application in page 1, fp1 = 1.35KHz,

ESR zero is much higher than the switching

frequency and fRHPZ=45.8KHz. Set fz1 to

3.18KHz and make the crossover frequency

8.5kHz, then R3=5kΩ and C3=10nF. Choose

5kΩ and 10nF.

In cases where the ESR zero is in a relatively

low frequency region and results in insufficient

gain margin, an optional capacitor (C5) (shown

in Figure 2) should be added. Then a pole,

formed by C5 and R3, should be placed at the

ESR zero to cancel the adverse effect.

fESRz

Layout Consideration

High frequency switching regulators require

very careful layout for stable operation and low

noise. Keep the high current path as short as

possible between the MOSFET drain, output

diode, output capacitor and GND pin for

minimal noise and ringing. The VCC capacitor

must be placed close to the VCC pin for best

decoupling. All feedback components must be

kept close to the FB pin to prevent noise

injection on the FB pin trace. The ground return

of the input and output capacitors should be

tied closed to the GND pin. See the MP3900

demo board layout for reference.

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