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MP8606 Datasheet(PDF) 12 Page - Monolithic Power Systems

Part # MP8606
Description  6A, 6.5V, Fast-Transient, Synchronous Step-Down Converter
PDF  17 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP8606 Datasheet(HTML) 12 Page - Monolithic Power Systems

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MP8606
– 6A, 6.5V SYNCHRONOUS STEP-DOWN CONVERTER
MP8606 Rev. 1.03
www.MonolithicPower.com
12
8/2/2013
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
Figure 7 shows a simplified external ramp
compensation (R4 and C4) for PWM mode, with
HS-FET off. Chose R1, R2, and C4 of the
external ramp to meet the following condition:
12
SW
4
1
2
RR
11
2
F
C
5
R
R

 
 

(4)
Where:
R4
C4
FB
C4
I
I
I
I
(5)
The downward slope of the VFB ripple can be
estimated as:
REF
SLOPE1
44
V
V
RC
(6)
Reducing either R4 or C4, as seen from equation
(6), can control some of the instability in PWM
mode. If the condition from equation (4) prevents
reductions to C4, then only reduce R4. VSLOPE1
has an expected range between 20V/ms to
40V/ms based on bench experiments.
The external ramp is not necessary for other
types of capacitors with higher ESR such as
POSCAPs.
Figure 8
—Simplified Circuit in PWM Mode
without External Ramp Compensation
Figure 8 shows the equivalent circuit in PWM
mode with the HS-FET off and without an
external ramp circuit. The ESR ripple dominates
the output ripple. The downward slope of the VFB
ripple is:
REF
SLOPE1
ESR V
V
L

(7)
Designing VSLOPE1—with a recommended range
between 15V/ms to 30V/ms based on bench
experiments
—requires using the minimum ESR
value of the output capacitor with a small-value
inductor.
An external ramp does not affect VSLOPE2 in skip
mode. Figure 9 shows an equivalent circuit with
HS-FET off and the current modulator regulating
the LS-FET. Instead, the downward slope of the
VFB ripple can be modeled with the following
equation that excludes IMOD:
REF
SLOPE2
1
2
OUT
V
V
R
R
C

(8)
Figure 9
—Simplified Circuit in Skip Mode
To keep the system stable during light load
condition, the values of the FB resistors should
be better in
the range of 5kΩ to 50kΩ. It is
recommended to keep the VSLOPE2 value between
0.4mV/ms to 0.8mV/ms.
When using a large-ESR capacitor on the output,
add a ceramic capacitor with a value of 10uF or
less to in parallel to minimize the effect of ESL.
Soft Start/Stop
MP8606
employs
a
soft
start/stop
(SS)
mechanism to ensure smooth output during
power up and power shut-down. When the EN
pin goes high, the internal SS voltage slowly
ramps up. The output voltage smoothly ramps up
with the SS voltage. Once SS voltage rises
above the VREF, it continues to ramp up while the
PWM comparator only compares the VREF with
the FB voltage. At this point, the soft start
finishes and it enters steady state operation. The



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