MP8606

– 6A, 6.5V SYNCHRONOUS STEP-DOWN CONVERTER

MP8606 Rev. 1.03

www.MonolithicPower.com

15

8/2/2013

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

© 2013 MPS. All Rights Reserved.

In the case of POSCAP or electrolytic capacitors,

the ESR dominates the impedance at the

switching frequency. The ramp voltage generated

from the ESR is high enough to stabilize the

system, and does not require an external ramp. A

minim

um ESR value of 12mΩ is recommended

to ensure stable operation of the converter. For

simplification,

the

output

ripple

can

be

approximated as:

OUT

OUT

OUT

ESR

SW

IN

VV

V

(1

) R

F

L

V





 





(18)

Maximum output capacitor limitation should be

also considered in design application. MP8606

has an around 1ms soft-start time period. If the

output capacitor value is too high, the output

voltage can

’t reach the design value during the

soft-start time, and then it will fail to regulate. The

limited approximately by:

O _ MAX

LIM _ AVG

OUT

ss

OUT

C

(I

I

) T / V







(19)

Inductor

The inductor is necessary to supply constant

current to the output load while being driven by

the

switched

input

voltage.

A

larger-value

inductor will result in less ripple current that will

result in lower output ripple voltage. However, a

larger-value inductor will have a larger physical

footprint, higher series resistance, and/or lower

saturation current. A good rule for determining

the inductance value is to design the peak-to-

peak ripple current in the inductor to be in the

range of 30% to 40% of the maximum output

current, and that the peak inductor current is

below the maximum switch current limit. The

inductance value can be calculated by:

OUT

OUT

SW

L

IN

VV

L

(1

)

F

I

V



 



(20)

Where ΔI

L

is the peak-to-peak inductor ripple

current.

The inductor should not saturate under the

maximum inductor peak current, where the peak

inductor current can be calculated by:

OUT

OUT

LP

OUT

SW

IN

VV

I

I

(1

)

2F

L

V





 



(21)

Design Example

Some

design

examples

and

recommended

maximum output capacitor value with typical

outputs are provided below:

Table 1

—V

(V)

(V)

R7

(

Ω)

R4

(

Ω)

C4

(

F)

R1

(

Ω)

R2

(

Ω)

(Hz)

5

1

169

k

442

k

100p

20

k

30

k

1000k

Table 2

— V

(V)

(V)

R7

(

Ω)

R4

(

Ω)

C4

(

F)

R1

(

Ω)

R2

(

Ω)

(Hz)

5

1.8

740k

442k

270p

42.2k

20k

400k

Table 3

— V

(V)

(V)

R7

(

Ω)

R4

(

Ω)

C4

(

F)

R1

(

Ω)

R2

(

Ω)

(Hz)

5

2.5

630k

442k

220p

52k

15k

650k

Table 4

— V

(V)

(V)

R7

(

Ω)

R4

(

Ω)

C4

(

F)

R1

(

Ω)

R2

(

Ω)

(Hz)

5

3.3

620k

390k

220p

50k

10k

860k

The detailed application schematic is shown in

Figure 10. The typical performance and circuit

waveforms have been shown in the Typical

Performance Characteristics section. For more

possible applications of this device, please refer

to related Evaluation Board Data Sheets.