FG896 datasheet(24/162 Pages) MICROSEMI

24 / 162 page

ProASIC3E DC and Switching Characteristics

2-10

Revision 13

Combinatorial Cells Contribution—PC-CELL

PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.



1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-11 on

page 2-11

FCLK is the global clock signal frequency.

Routing Net Contribution—PNET

PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design.

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.



1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-11 on

page 2-11

FCLK is the global clock signal frequency.

I/O Input Buffer Contribution—PINPUTS

PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK

NINPUTS is the number of I/O input buffers used in the design.



2 is the I/O buffer toggle rate—guidelines are provided in Table 2-11 on page 2-11.

FCLK is the global clock signal frequency.

I/O Output Buffer Contribution—POUTPUTS

POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK

NOUTPUTS is the number of I/O output buffers used in the design.



2 is the I/O buffer toggle rate—guidelines are provided in Table 2-11 on page 2-11.



1 is the I/O buffer enable rate—guidelines are provided in Table 2-12 on page 2-11.

FCLK is the global clock signal frequency.

RAM Contribution—PMEMORY

PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3

NBLOCKS is the number of RAM blocks used in the design.

FREAD-CLOCK is the memory read clock frequency.



2 is the RAM enable rate for read operations—guidelines are provided in Table 2-12 on

page 2-11

FWRITE-CLOCK is the memory write clock frequency.



3 is the RAM enable rate for write operations—guidelines are provided in Table 2-12 on

page 2-11

PLL Contribution—PPLL

PPLL = PAC13 + PAC14 * FCLKOUT

FCLKOUT is the output clock frequency.1

1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the

PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output

clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution.

FG896 Datasheet(PDF) 24 Page - Microsemi Corporation

FG896 Datasheet(HTML) 24 Page - Microsemi Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL