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FG896 Datasheet(PDF) 64 Page - Microsemi Corporation |
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FG896 Datasheet(HTML) 64 Page - Microsemi Corporation |
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64 / 162 page ![]() ProASIC3E DC and Switching Characteristics 2-50 Revision 13 Timing Characteristics B-LVDS/M-LVDS Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard to high-performance multipoint bus applications. Multidrop and multipoint bus configurations may contain any combination of drivers, receivers, and transceivers. Microsemi LVDS drivers provide the higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The drivers require series terminations for better signal quality and to control voltage swing. Termination is also required at both ends of the bus since the driver can be located anywhere on the bus. These configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with appropriate terminations. Multipoint designs using Microsemi LVDS macros can achieve up to 200 MHz with a maximum of 20 loads. A sample application is given in Figure 2-23. The input and output buffer delays are available in the LVDS section in Table 2-80. Example: For a bus consisting of 20 equidistant loads, the following terminations provide the required differential voltage, in worst-case Industrial operating conditions, at the farthest receiver: RS =60 and RT =70 , given Z0 =50 (2") and Zstub =50 (~1.5"). Table 2-80 • LVDS Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Speed Grade tDOUT tDP tDIN tPY Units Std. 0.66 1.87 0.04 1.82 ns –1 0.56 1.59 0.04 1.55 ns –2 0.49 1.40 0.03 1.36 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. Figure 2-23 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers ... RT RT BIBUF_LVDS R + - T + - R + - T + - D + - EN EN EN EN EN Receiver Transceiver Receiver Transceiver Driver RS RS RS RS RS RS RS RS RS RS Zstub Zstub Zstub Zstub Zstub Zstub Zstub Zstub Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 Z0 |
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