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MP38900 Datasheet(PDF) 13 Page - Monolithic Power Systems

Part # MP38900
Description  High Efficiency, Fast Transient, 10A, 16V Synchronous Step-down Converter In a Tiny QFN20 Package
PDF  23 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP38900 Datasheet(HTML) 13 Page - Monolithic Power Systems

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MP38900/MP38900-B–HIGHEFFICIENCY,FASTTRANSIENTSYNCHRONOUSSTEP-DOWNCONVERTER
MP38900/MP38900-B Rev. 1.1
www.MonolithicPower.com
13
6/25/2012
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
IN
OUT
OUT
OUT
SW
IN
(V
V
) V
I
2L F
V


(2)
It turns into PWM mode once the output current
exceeds the critical level. After that, the switching
frequency stays fairly constant over the output
current range.
Switching Frequency
Constant-on-time (COT) control is used in the
MP38900/MP38900-B and there is no dedicated
oscillator in the IC. The input voltage is feed-
forwarded to the on-time one-shot timer through
the resistor R7. The duty ratio is kept as VOUT/VIN.
Hence, the switching frequency is fairly constant
over the input voltage range.
The switching
frequency can be set as follows:
(ns)
t
(V)
V
(V)
V
0.45
(V)
V
)
R7(k
12
10
kHz
f
DELAY2
OUT
IN
IN
6
SW
)
(
(3)
Where tDELAY2 is the comparator delay. It’s about
40ns.
MP38900/MP38900-B is optimized to operate at
high switching frequency with high efficiency.
High switching frequency makes it possible to
utilize small sized LC filter components to save
system PCB space.
Jitter and FB Ramp Slope
Figure 5 and Figure 6 show jitter occurring in
both PWM mode and skip mode. When there is
noise in the VFB downward slope, the ON time of
the HS-FET driver deviates from its intended
location and produces jitter. It is necessary to
understand that there is a relationship between a
system’s stability and the steepness of the VFB
ripple’s downward slope. The slope steepness of
the VFB ripple dominates in noise immunity. The
magnitude of the VFB ripple doesn’t affect the
noise immunity directly.
V
RE F
V
FB
HS D river
VNOISE
J itter
V
S L O PE1
Figure 5: Jitter in PWM Mode
V
FB
HS D river
Jitter
V
REF
V
SL O P E 2
VNOISE
Figure 6: Jitter in Skip Mode
Ramp with Large ESR Cap
In the case of POSCAP or other types of
capacitor with larger ESR is applied as output
capacitor. The ESR ripple dominates the output
ripple, and the slope on the FB is quite ESR
related. Figure 7 shows an equivalent circuit in
PWM mode with the HS-FET off and without an
external ramp circuit. Turn to application
information section for design steps with large
ESR caps.
Figure 7: Simplified Circuit in PWM Mode
without External Ramp Compensation
To realize the stability when no external ramp is
used, usually the ESR value should be chosen
as follow:



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