AM53CF96JC datasheet(28/76 Pages) AMD

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P R E L I M I N A R Y

AMD

Am53CF94/Am53CF96

Current FIFO/Internal State Register (07H) Read

Current FIFO/Internal State Register

CFISREG

Address: 07H

Type: Read

76543

210

IS2

IS1

IS0

CF4

CF3

CF2

CF1

CF0

0000

000

Internal State 2:0

Current FIFO 4:0

17348B-26

This register has two fields, the Current FIFO field and

the Internal State field.

CFISREG – Bits 7:5 – IS 2:0 – Internal State 2:0

The Internal State Register (ISREG) tracks the progress

of a sequence-type command.

The IS 2:0 bits are duplicated from the IS 2:0 field in the

Internal State Register (ISREG) in the normal mode. If

the device is in the test mode, (see CNTLREG1, bit 3)

IS 0 is set to indicate that the offset value is non-zero.

A non-zero value indicates that synchronous data

transfer can continue. A zero value indicates that the

synchronous offset count has been reached and no

more data can be transferred until an acknowledge is

received.

CFISREG – Bits 4:0 – CF 4:0 – Current FIFO 4:0

The CF 4:0 bits are the binary coded value of the num-

ber of bytes in the FIFO. These bits should not be read

when the device is transferring data since this count

may not be stable.

Synchronous Offset Register (07H) Write

Synchronous Offset Register

SOFREG

Address: 07H

Type: Write

76543

210

SO3

SO2

SO1

SO0

RAD1

RAD0

RAA1

RAA0

0000

000

REQ/ACK Assertion 1:0

Synchronous Offset 3:0

REQ/ACK Deassertion 1:0

17348B-27

The Synchronous Offset Register (SOFREG) controls

REQ/ACK deassertion/assertion delay and stores a

4-bit count of the number of bytes that can be sent to

(or received from) the SCSI bus during synchronous

transfers without an

ACK (or REQ). Bytes exceeding

the threshold will be sent one byte at a time

(asynchronously). That is, each byte will require an

ACK/REQ handshake. To set up an asynchronous

transfer, the SOFREG is set to zero. The SOFREG is set

to zero after a hard or soft reset.

SOFREG – Bits 7:6 – RAD 1:0

These bits may be programmed to control the deasser-

tion delay of the

REQ and ACK signals during synchro-

nous transfers. Deassertion delay is expressed as input

clock cycles, and depends on the implementation of

FASTCLK. (See CNTLREG3, bit 3)

AM53CF96JC Datasheet(PDF) 28 Page - Advanced Micro Devices

AM53CF96JC Datasheet(HTML) 28 Page - Advanced Micro Devices

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