AM53CF96JC datasheet(32/76 Pages) AMD

32 / 76 page

P R E L I M I N A R Y

AMD

Am53CF94/Am53CF96

and then issue an information transfer command. The

first word the device will write to the memory (via DMA)

will consists of the lower byte from the DALREG and the

upper byte from the first byte received from the

SCSI bus.

The DAE bit must be set before the phase changes to

the Synchronous Data-In. The DAE bit is reset to zero by

a hard or soft reset or by writing the DALREG when in-

terrupted in the Synchronous Data-In phase.

CNTLREG2 – Bit 6 – ENF – Enable Features

A software or hardware reset will clear this bit to its de-

fault value of ‘0’; a SCSI reset will leave this bit unaf-

fected. When set to a value of ‘1’, this bit activates the

following product enhancements:

1) The Current Transfer Count Register High (0EH)

will be enabled, extending the transfer counter from

16 to 24 bits to allow for larger transfers.

2) Following a chip or power on reset, up until the point

where the Current Transfer Count Register High

(0EH) is loaded with a value, it is possible to read

the part-unique ID from this register.

3) The SCSI phase will be latched at the completion of

each command by bits 2:0 in the Status Register

(STATREG). When this bit is ‘0’, the Status Register

(STATREG) will reflect real-time SCSI phases.

4) The enable signal for the differential drivers may be

delayed to avoid bus contention on the SCSI

differential lines when the direction for

I/O is

switching. When the SCSI bus changes direction

from input to output, the output drivers are not

asserted for two clock cycles to avoid bus

contention. When the bus changes from output to

input,

SDC7:0 are given time to switch direction

before the SCSI drivers are asserted.

CNTLREG2 – Bit 5 – SBO – Select Byte Order

The SBO bit is used only when the BUSMD 1:0 = 10 to

enable or disable the byte control on the DMA interface.

When SBO is set and the BUSMD 1:0 = 10, the byte con-

trol inputs BHE and AS0 control the byte positions.

When SBO is reset the byte control inputs BHE and AS0

are ignored.

CNTLREG2 – Bit 4 – TSDR – Tri-State DMA

Request

The TSDR bit when set sends the DREQ output signal to

high impedance state and the device ignores all activity

on the DMA request (DREQ) input. This is useful for

wiring-OR several devices that share a common DMA

request line. When the TSDR bit is reset the DREQ

output is driven to TTL levels.

CNTLREG2 – Bit 3 – S2FE – SCSI-2 Features

Enable

The S2FE bit allows the device to recognize two SCSI-2

features: the extended message feature and the

Group 2 command recognition. (These features can

also be controlled independently by bits 6:5 in

CNTLREG3).

Extended Message Feature: When the S2FE bit is set

and the device is selected with attention, the device will

monitor the

ATN signal at the end of the first message

byte. If the

ATN signal is active, the device will request

two more message bytes before switching to the com-

mand phase. If the

ATN signal is inactive the device will

switch to the Command phase. When the S2FE bit is re-

set as a Target the device will request a single message

byte. As an Initiator, the device will abort the selection

sequence if the Target does not switch to the Command

phase after receiving a single message byte.

Group 2 Command Recognition: When the S2FE bit is

set, the GCV (Group Code Valid) bit in the STATREG

(04H) is set, allowing the Group 2 commands to be rec-

ognized as 10 byte commands. When the S2FE bit is

reset, the GCV bit in the STATREG is not set, and the

device will interpret the Group 2 commands as reserved

commands and will request 6 byte commands.

CNTLREG2 – Bit 2 – ACDPE – Abort on Command/

Data Parity Error

The ACDPE bit when set allows the device to abort a

command or data transfer when a parity error is de-

tected. When the ACDPE bit is reset parity error is ig-

nored.

CNTLREG2 – Bit 1 – PGRP – Pass Through/Gener-

ate Register Parity

The PGRP bit, when set, allows parity from DMAP1–0 to

pass during register writes to the FIFO. Enabling this bit

also causes parity checking as data is unloaded from

the FIFO to the SCSI bus.

When this bit is reset to zero, parity is generated for reg-

ister writes to the FIFO, however no additional checking

will be done as FIFO data is unloaded to the SCSI bus

unless the PGDP bit is set.

CNTLREG2 – Bit 0 – PGDP – Pass Through/Gener-

ate Data Parity

The PGDP bit, when set, allows parity from DMAP1–0 to

pass during DMA writes to the FIFO. Parity checking will

also be performed as data is unloaded from the FIFO to

the SCSI bus.

When this bit is reset to zero, parity is generated during

DMA Writes to the FIFO, however no additional check-

ing will be done as FIFO data is unloaded, unless the

PGRP bit is set.

AM53CF96JC Datasheet(PDF) 32 Page - Advanced Micro Devices

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