AM53CF96JC datasheet(38/76 Pages) AMD

38 / 76 page

P R E L I M I N A R Y

AMD

Am53CF94/Am53CF96

COMMAND DESCRIPTION

Initiator Commands

Initiator commands are executed by the device when

it is in the Initiator mode. If the device is not in the Initia-

tor mode and an Initiator command is received the

device will ignore the command, generate an Invalid

Command interrupt and clear the Command Register

(CMDREG).

Should the Target disconnect from the SCSI bus by

deasserting the

BSY signal line while the ESC (Initiator)

is waiting for the Target to assert

REQ, a Disconnected

Interrupt will be issued 1.5 to 3.5 clock cycles following

BSY going false.

Upon receipt of the last byte during Msg In phase,

ACK

will remain asserted to prevent the Target from issuing

any additional bytes, while the Initiator decides to ac-

cept/reject the message. If non-DMA commands are

used, the last byte signals the FIFO is empty. If DMA

commands are used, the transfer counter signals the

last byte.

If parity checking is enabled in the Initiator mode and an

error is detected,

ATN will be asserted for the erroneous

byte before deasserting

ACK. An exception to this is fol-

lowing a phase change to Synchronous Data In.

To program Synchronous Transfer, the Synchronous

Offset Register (SOFREG) must be set to a non-zero

value. While in this mode, if the phase changes to Data

In, the DMA interface is disabled, and parity generation

is delayed. The Data In phase will latch the FIFO flags to

indicate the number of bytes in the FIFO, clear the FIFO,

load the FIFO with the first byte of Data In, generate an

interrupt, and continue to load the FIFO with incoming

bytes up to the synchronous offset.

Information Transfer Command

(Command Code 10H/90H)

The Information Transfer command is used to transfer

information bytes over the SCSI bus. This command

may be issued during any SCSI Information Transfer

phase. Synchronous data transmission requires use of

the DMA mode.

The device will continue to transfer information until it is

terminated by any one of the following conditions:

s The Target changes the SCSI bus phase before the

expected number of bytes are transferred. The

device clears the Command Register (CMDREG),

and generates a service interrupt when the Target

asserts

REQ.

s Transfer is successfully complete. If the phase is

Message Out, the device deasserts

ATN before

asserting

ACK for the last byte of the message.

When the Target asserts

REQ, a service interrupt is

generated.

s In the Message In phase when the device receives

the last byte. The device keeps the

ACK signal

asserted and generates a Successful Operation

interrupt.

During synchronous data Transfers the Target may

send up to the maximum synchronous threshold num-

ber of

REQ pulses to the Initiator. If it is the Synchronous

Data-In phase then the Target sends the data and the

REQ pulses. These bytes are stored by the Initiator in

the FIFO as they are received.

Information Transfer Command, when issued during the

following SCSI phases and terminated in synchronous

data phases, is handled as described below:

s Message In/Status Phase – When a phase change

to Synchronous Data-In or Synchronous Data-Out is

detected by the device, the Command Register

(CMDREG) is cleared and the DMA interface is

disabled to disallow any transfer of data phase bytes.

If the phase change is to Synchronous Data-In and

bad parity is detected on the data bytes coming in, it

not

reported

since

the

Status

(STATREG) will report the status of the command

just completed. The parity error flag and the

ATN

signal will be asserted when the Transfer Information

command begins execution.

s Message Out/Command Phase – When a phase

change to Synchronous Data-In or Synchronous

Data-Out is detected by the device, the Command

interface is disabled to disallow any transfer of data

phase bytes. If the phase change is to Synchronous

Data-In and bad parity is detected on the data bytes

coming in, it is not reported since the Status Register

(STATREG) will report the status of the command

just completed. The parity error flag and the

ATN

signal will be asserted when the Transfer Information

command begins execution. The FIFO Register

(FFREG) will be latched and will remain in that

condition until the next command begins execution.

The value in the FFREG indicates the number of

bytes in the FIFO when the phase changed to

Synchronous Data-In. These bytes are cleared from

the FIFO, which now contains only the incoming data

bytes.

s In the Synchronous Data-Out phase, the threshold

counter is incremented as

REQ pulses are received.

The transfer is completed when the FIFO is empty

and the Current Transfer Count Register (CTCREG)

is zero. The threshold counter will not be zero.

s In the Synchronous Data-In phase, the Current

Transfer Count Register (CTCREG) is decre-

mented as bytes are read from the FIFO rather than

being decremented when the bytes are being written

to the FIFO. The transfer is completed when Current

Transfer Count Register (CTCREG) is zero but the

FIFO may not be empty.

AM53CF96JC Datasheet(PDF) 38 Page - Advanced Micro Devices

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