AM53CF96JC datasheet(33/76 Pages) AMD

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P R E L I M I N A R Y

AMD

Am53CF94/Am53CF96

Control Register Three

CNTLREG3

Address: 0CH

Type: Read/Write

765

210

ADID

CHK

QTAG

G2CB

FAST

SCSI

FAST

CLK

LBTM

MDM

BS8

00000

000

QTAG Control

Group 2 Command Block

FASTSCSI

FASTCLK

Last Byte Transfer Mode

Modify DMA Mode

Burst Size 8

Additional ID Check

Control Register Three (0CH) Read/Write

17348B-32

CNTLREG3 – Bit 7 – ADIDCHK – Additional ID

Check

Enables additional check on ID message during bus-

initiated Select or Reselect with

ATN. The ESC will

check bits 7, and bits 5:3 in the first byte of the ID mes-

sage during Selection of Reselection. An interrupt will

be generated if bit 7 is ‘0’, or if bits 5, 4, or 3 are ‘1’.

CNTLREG3 – Bit 6 – QTAG – QTAG Control

This bit controls the Queue Tag feature in the ESC.

When enabled, the ESC is capable of receiving 3-byte

messages during bus-initiated Select/Reselect with

ATN. (Bit 3, Control Register Two also enables this fea-

ture). The 3-byte message consists of one byte Identify

Message and two bytes of Queue Tag message. The

ESC will check the second byte for values of 20h, 21h,

and 22h. If this condition is not satisfied, the sequence

halts and the ESC generates an interrupt.

When the QTAG feature is not enabled, the ESC halts

the Selected with

ATN sequence following the receipt of

one ID message byte if

ATN is still true.

CNTLREG3 – Bit 5 – G2CB – Group 2 Command

Block

When this bit is set, the ESC is capable of recognizing

10-byte Group 2 Commands as valid CDBs (Command

Descriptor Blocks). (This feature is also controlled by

bit 3 of CNTLREG2). When this feature is enabled, the

Target receives 10 bytes of Group 2 commands, and

sets the group code valid bit (bit 3) in Status Register

(STATREG). When this feature is disabled, the Target

receives only 6 bytes of command code, and does not

set bit 3 in register (04H).

This bit may be programmed in conjunction with bit 6

(described above) to send 1 or 3 byte messages with 6

or 10 byte CDBs. The following table illustrates the

transmission options:

CNTLREG3 – Bit 4 – FASTSCSI – Fast SCSI

CNTLREG3 – Bit 3 – FASTCLK – Fast SCSI

Clocking

These bits configure the ESC’s state machine to support

both Fast SCSI timings and SCSI-1 timings. These bits

will affect the SCSI transfer rate, and must be consid-

ered in conjunction with the ESC’s clock frequency and

mode of operation.

CNTLREG3

CNTLREG2

Bit 6

Bit 5

Bit 3

Enabled

QTAG

G2CB

S2FE

Features

––

10-byte CDB,

3-byte

message

3-byte

message

10-byte CDB

10-byte CDB,

3-byte

message

Features

disabled

–– = don’t care

AM53CF96JC Datasheet(PDF) 33 Page - Advanced Micro Devices

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