AM79C960KCW datasheet(34/127 Pages) AMD

34 / 127 page

P R E L I M I N A R Y

AMD

1-376

Am79C960

16907B-7

Initialization

Block

24-Bit Base Address

Pointer to

Initialization Block

IADR[15:0]

IADR[23:16]

RES

CSR1

CSR2

TDRA[15:0]

MODE

PADR[15:0]

PADR[31:16]

PADR[47:32]

LADRF[15:0]

LADRF[31:16]

LADRF[47:32]

LADRF[63:48]

RDRA[15:0]

RLEN

RES

RDRA[23:16]

TLEN RES

TDRA[23:16]

RCV

Buffers

RX DESCRIPTOR RINGS

RMD0

RMD1 RMD2 RMD3

RCV Descriptor

Ring

•

1st desc.

start

2nd desc.

start

RMD0

XMT

Buffers

RX DESCRIPTOR RINGS

TMD0

TMD1 TMD2 TMD3

RX DESCRIPTOR RINGS

XMT Descriptor

Ring

•

1st desc.

start

2nd desc.

start

TMD0

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

Data

Buffer

16907B-7

Initialization Block and Descriptor Rings

Polling

When there is no channel activity and there is no pre- or

post-receive or transmit activity being performed by the

PCnet-ISA controller, then the PCnet-ISA controller will

periodically poll the current receive and transmit de-

scriptor entries in order to ascertain their ownership. If

the DPOLL bit in CSR4 is set, then the transmit polling

function is disabled.

A typical polling operation consists of the following: The

PCnet-ISA controller will use the current receive de-

scriptor address stored internally to vector to the

appropriate Receive Descriptor Table Entry (RDTE). It

will then use the current transmit descriptor address

(stored internally) to vector to the appropriate Transmit

Descriptor Table Entry (TDTE). These accesses will be

made to RMD1 and RMD0 of the current RDTE and

TMD1 and TMD0 of the current TDTE at periodic polling

intervals. All information collected during polling activity

will be stored internally in the appropriate CSRs. (i.e.

CSR18–19, CSR20–21, CSR40, CSR42, CSR50,

CSR52). UnOWNed descriptor status will be internally

ignored.

AM79C960KCW Datasheet(PDF) 34 Page - Advanced Micro Devices

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