AM79C960KCW datasheet(53/127 Pages) AMD

53 / 127 page

P R E L I M I N A R Y

AMD

1-395

Am79C960

The PCnet-ISA controller will perform 8-bit ISA bus cy-

cle operation for all resource (registers, PROMs,

SRAM) if

SBHE has been left unconnected, such as in

the case of an 8-bit system like the PC/XT.

The

BPCS signal generated by the PCnet-ISA controller

is three 20 MHz clock cycles wide (150 ns). Including de-

lays, the Boot PROM has 120 ns to respond to the

BPCS

signal from the PCnet-ISA controller. This signal is in-

tended to be connected to the

CS pin on the boot

PROM, with the PROM

OE pin tied to ground. The ac-

cess time of the boot PROM must be 120 ns or faster

when 16-bit ISA memory cycles are to be supported.

Static RAM Cycles

The shared memory SRAM is an 8-bit device connected

to the PCnet-ISA controller Private Bus, and can occupy

up to 64 Kbytes of address space. In Shared Memory

Mode, an external address comparator is responsible

for asserting

SMAM to the PCnet-ISA controller. SMAM

is intended to be a perfect decode of the SRAM address

space, i.e.

REF, LA17-23, SA16 for 64 Kbytes of SRAM.

The LA signals must be latched by BALE in order to pro-

vide a stable decode for

SMAM. The PCnet-ISA

controller assumes 16-bit ISA memory bus cycles for

the SRAM, so this same logic must assert

MEMCS16 to

the ISA bus if 16-bit bus cycles are to be supported.

A 16-bit SRAM bus cycle begins with the Permanent

Master driving the addresses valid,

REF inactive, and

either

MEMR or MEMW active. (AEN is not involved in

memory cycles). External hardware would assert

SMAM and MEMCS16. The PCnet-ISA controller de-

tects this combination of signals and initiates the SRAM

access.

In a write cycle, the PCnet-ISA controller stores the data

into an internal holding register, allowing the ISA bus cy-

cle to finish normally. The data in the holding register will

then be written to the SRAM without the need for ISA

bus control. In the event the holding register is already

filled with unwritten SRAM data, the PCnet-ISA control-

ler will extend the ISA write cycle by driving IOCHRDY

LOW until the unwritten data is stored in the SRAM. The

current ISA bus cycle will then complete normally.

In a read cycle, the PCnet-ISA controller arbitrates for

the Private Bus. If it is unavailable, the PCnet-ISA con-

troller drives IOCHRDY LOW. When the Private Data

Bus is available, the PCnet-ISA controller asserts the

Address Buffer Output Enable (

ABOE) signal to drive

the upper 6 bits of the Private Address Bus from the Sys-

tem Address Bus. The PCnet-ISA controller itself drives

the lower 10 bits of the Private Address Bus from the

System Address Bus and compares the 16 bits of ad-

dress on the Private Address Bus with that of a SRAM

data word held in an internal pre-fetch buffer.

If the address does not match that of the prefetched

SRAM data, then the PCnet-ISA controller drives

IOCHRDY LOW and reads two bytes from the SRAM.

The PCnet-ISA controller then proceeds as though the

addressed data location had been prefetched.

If the internal prefetch buffer contains the correct data,

then the pre-fetch buffer data is driven on the System

Data bus. If IOCHRDY was previously driven LOW due

to either Private Data Bus arbitration or SRAM access,

then it is released HIGH. The PCnet-ISA controller re-

mains in this state until

MEMR is de-asserted, at which

time the PCnet-ISA controller performs a new prefetch

of the SRAM. In this way memory read wait states can

be minimized.

The PCnet-ISA controller performs prefetches of the

SRAM between ISA bus cycles. The SRAM is

prefetched in an incrementing word address fashion.

Prefetched data are invalidated by any other activity on

the Private Bus, including Shared Memory Writes by

either the ISA bus or the network interface, and also ad-

dress and boot PROM reads.

The only way to configure the PCnet-ISA controller for

8-bit ISA bus cycles for SRAM accesses is to configure

the entire PCnet-ISA controller to support only 8-bit ISA

bus cycles. This is accomplished by leaving the

SBHE

pin disconnected. The PCnet-ISA controller will perform

8-bit ISA bus cycle operation for all resources (registers,

PROMs, SRAM) if

SBHE has never been driven active

since the last RESET, such as in the case of an 8-bit sys-

tem like the PC/XT. In this case, the external address

decode logic must not assert

MEMCS16 to the ISA bus,

which will be the case if

MEMCS16 is left unconnected.

It is possible to manufacture a dual 8/16 bit PCnet-ISA

controller adapter card, as the

MEMCS16 and SBHE

signals do not exist in the PC/XT environment.

At the memory device level, each SRAM Private Bus

read cycle takes two 50 ns clock periods for a maximum

read access time of 75 ns. The timing looks like this:

16907B-10

XTAL1

(20 MHz)

Address

SROE

Static RAM Read Cycle

AM79C960KCW Datasheet(PDF) 53 Page - Advanced Micro Devices

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