AM79C960KCW datasheet(64/127 Pages) AMD

64 / 127 page

P R E L I M I N A R Y

AMD

1-406

Am79C960

Read/write accessible only when

STOP bit is set.

CSR12: Physical Address Register, PADR[15:0]

Bit

Name

Description

15-0 PADR[15:0]

Physical

Address

PADR[15:0]. Undefined until in-

itialized either automatically by

loading the initialization block or

directly by an I/O write to this

transmitted PADR[0] first and

PADR[47] last.

Read/write accessible only when

STOP bit is set.

CSR13: Physical Address Register, PADR[31:16]

Bit

Name

Description

15-0 PADR[31:16]

Physical

Address

PADR[31:16]. Undefined until in-

itialized either automatically by

loading the initialization block or

directly by an I/O write to this

transmitted PADR[0] first and

PADR[47] last.

Read/write accessible only when

STOP bit is set.

CSR14: Physical Address Register, PADR[47:32]

Bit

Name

Description

15-0 PADR[47:32]

Physical

Address

PADR[47:32]. Undefined until in-

itialized either automatically by

loading the initialization block or

directly by an I/O write to this

transmitted PADR[0] first and

PADR[47] last.

Read/write accessible only when

STOP bit is set.

CSR15: Mode Register

Bit

Name

Description

This register’s fields are loaded

during the PCnet-ISA controller

initialization routine with the cor-

responding Initialization Block

values. The register can also be

loaded directly by an I/O write.

Activating the RESET pin clears

all bits of CSR15 to zero.

PROM

Promiscuous Mode.

When PROM = “1”, all incoming

receive frames are accepted.

Read/write accessible only when

STOP bit is set.

DRCVBC

DisableReceive Broadcast .When

set, disables the PCnet-ISA con-

troller from responding to broad-

cast messages. Used for proto-

cols that do not support broad-

cast addressing, except as a

function of multicast. DRCVBC is

cleared by activation of the

RESET pin (broadcast mes-

sages will be received).

Read/write accessible only when

STOP bit is set.

DRCVPA

Disable Receive Physical Ad-

dress. When set, the physical

address detection (Station or

node ID) of the PCnet-ISA con-

troller will be disabled. Frames

addressed to the nodes individ-

ual physical address will not be

recognized (although the frame

may be accepted by the EADI

mechanism).

Read/write accessible only when

STOP bit is set.

DLNKTST

Disable

Link

Status.

When

DLNKTST = “1”, monitoring of

Link Pulses is disabled. When

DLNKTST = “0”, monitoring of

Link Pulses is enabled. This bit

only has meaning when the

10BASE-T network interface is

selected.

Read/write accessible only when

STOP bit is set.

DAPC

Disable Automatic Polarity Cor-

rection. When DAPC = “1”, the

10BASE-T receive polarity rever-

sal

algorithm

disabled.

Likewise, when DAPC = “0”, the

polarity reversal algorithm is en-

abled.

This bit only has meaning when

the 10BASE-T network interface

is selected.

Read/write accessible only when

STOP bit is set.

MENDECL

MENDEC Loopback Mode. See

the description of the LOOP bit in

CSR15.

Read/write accessible only when

STOP bit is set.

LRT/TSEL

Low Receive Threshold (T-MAU

Mode only)

AM79C960KCW Datasheet(PDF) 64 Page - Advanced Micro Devices

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