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AM79C960KCW Datasheet(PDF) 98 Page - Advanced Micro Devices |
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AM79C960KCW Datasheet(HTML) 98 Page - Advanced Micro Devices |
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98 / 127 page  P R E L I M I N A R Y AMD 1-440 Am79C960 SWITCHING CHARACTERISTICS: GPSI Notes: 1. CLSN must be asserted for a continuous period of 110 ns or more. Assertion for less than 110 ns period may or may not result in CLSN recognition. 2. RCLK should meet jitter requirements of IEEE 802.3 specification. 3. CLSN assertion before 51.2 µs will be indicated as a normal collision. CLSN assertion after 51.2 µs will be considered as a Late Receive Collision. Parameter Symbol Parameter Description Test Conditions Min Max Unit Transmit Timing tGPT1 TCLK Period (802.3 Compliant) 99.99 100.01 ns tGPT2 TCLK HIGH Time 40 60 ns tGPT3 TX and TENA Delay from ↑ TCLK 0 70 ns tGPT4 RENA Setup Before ↑ TCLK (Last Bit) 210 ns tGPT5 RENA Hold After ↓ TENA 0 ns tGPT6 CLSN Active Time to Trigger Collision (Note 1) 110 ns tGPT7 CLSN Active to ↓ RENA to Prevent LCAR Assertion 0 ns tGPT8 CLSN Active to ↓ RENA for SQE Hearbeat Window 0 4.0 µs Tgpt9 CLSN Active to ↑ Rena for Normal Collision 0 51.2 µs Receive Timing tGPR1 RCLK Period (Note 2) 80 120 ns tGPR2 RCLK HIGH Time (Note 2) 30 80 ns tGPR3 RCLK LOW Time (Note 2) 30 80 ns tGPR4 RX and RENA Setup to ↑ RCLK 15 ns tGPR5 RX Hold After ↑ RCLK 15 ns tGPR6 RENA Hold After ↓ RCLK 0 ns tGPR7 CLSN Active to First ↑ RCLK (Collision Recognition) 0 ns tGPR8 CLSN Active to ↑ RCLK for Address Type Designation Bit (Note 3) 51.2 µs tGPR9 CLSN Setup to Last ↑ RCLK for Collision Recognition 210 ns tGPR10 CLSN Active 110 ns tGPR11 CLSN Inactive Setup to First ↑ RCLK 300 ns tGPR12 CLSN Inactive Hold to Last ↑ RCLK 300 ns |
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