TAS5076 datasheet(25/64 Pages) TI

25 / 64 page

Architecture Overview

SLES090A—November 2003—Revised January 2004

TAS5076

Table 2−10. De-Emphasis Filter Characteristics

DEM_SEL2 (MSB)

DEM_SEL1

DESCRIPTION

De-emphasis disabled

De-emphasis enabled for Fs = 48 kHz

De-emphasis enabled for Fs = 44.1 kHz

De-emphasis enabled for Fs = 32 kHz

Following the change of state of the de-emphasis bits, the PWM outputs go into the soft mute state. After 128

LRCLK periods for initialization, the PWM outputs are driven to the normal (unmuted) mode.

−10

3.18 (50

µs)

10.6 (15

µs)

f − Frequency − kHz

De-Emphasis

Figure 2−11. De-Emphasis Filter Characteristics

2.4

Pulse-Width Modulator (PWM)

The TAS5076 contains six channels of high performance digital Equibit PWM modulators that are designed

to drive switching output stages (back ends) in both single-ended (SE) and H-bridge (bridge tied load)

configuration. The TAS5076 device uses noise shaping and sophisticated error correction algorithms to

achieve high power efficiency and high-performance digital audio reproduction.

The PWM provides six pseudodifferential outputs to drive six monolithic power stages (such as TAS5110) or

six discrete differential power stages using gate drivers (such as the TAS5182) and MOSFETs in single-ended

or bridged configurations. The TAS5076 also provides a high-performance differential output that can be used

to drive an external analog headphone amplifier.

2.4.1 Clipping Indicator

The clipping output is designed to indicate clipping. When any of the six PWM outputs exceeds the maximum

allowable amplitude, the clipping indicator is asserted. The clipping indicator is cleared every 10 ms.

2.4.2 Error Recovery

Error recovery is used to provide error management and to permit the PWM output to be reset while preserving

all intervolume, interchannel delay, dc offsets, and the other internal settings. Error recovery is initiated by

bringing the ERR_RCVRY terminal low for a minimum 5 MCLK_IN cycles or by setting the error recovery bit

in control register 1. Error recovery is a level-sensitive signal.

The device also performs an error recovery automatically:

•

When the speed configuration is changed to normal, double, or quad speed

•

Following a change in the serial data bus interface configuration

When ERR_RCVRY is brought low, all valid signals go low, and the PWM_P and PWM_M outputs go low. If

there are any pending speed configurations, these changes are then performed. When ERR_RCVRY is

brought high, a delay of 4 ms to 5 ms is performed before the system starts the output re-initialization

sequence. After the initialization time, the TAS5076 begins normal operation. During error recovery, all

controls and device settings that were not updated are maintained in their current configurations.

To permit error recovery to be used to provide TAS5100 error management and recovery, the delay between

the start of (falling edge) error recovery and the falling edge of valid 1 though valid 6 is selectable. This delay

can be selected to be either 6

µs or 47 µs.

TAS5076 Datasheet(PDF) 25 Page - Texas Instruments

TAS5076 Datasheet(HTML) 25 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Datasheet Download

Link URL