SCANSTA111 datasheet(22/38 Pages) TI

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SCANSTA111

SNLS060K – AUGUST 2001 – REVISED APRIL 2013

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PARAMETERIZED DESIGN (HDL)

In order to support a large number of applications, the 'STA111 HDL is parameterized as described:

•

Number of Local Scan Ports (LSPs): The 'STA111 HDL is able to simulate/synthesize a device that

contains from 1 to 8 LSPs. LSP0 through LSP4 are controlled via Mode Register0 and LSP5 through LSP7 are

controlled via Mode Register1. The silicon version of the 'STA111 is synthesized with three LSPs, LSP0

through LSP2.

•

Number of Address Pins: The 'STA111 has a selectable number of address bits (S0 - Sn, where n can

range from 5 to 7). Addresses 3A through 3F hex are reserved for address interrogation, broadcast and multi-

cast addressing. The silicon version of the 'STA111 is synthesized with seven address pins.

•

Pass-Through Pins: Each of the LSPs (0-n) may selectively have or not have Pass-through pins. Pass-

through pins are described in more detail below. The silicon version of the 'STA111 is synthesized with Pass-

through pins on LSP0 and LSP1.

•

Number/Type of GPIO bits: The 'STA111 has both dedicated and shared GPIO (General Purpose I/O).

Each dedicated group of GPIO bits supports from 0 to 4 dedicated inputs and 0 to 4 dedicated outputs. There

are provisions for specifying the default (power-up) value. TMS(0-n), TDO(0-n) and TDI(0-n) are also dual purpose

pins functioning as LSP or GPIO. TMSn and TDOn are outputs, TDIn is an input in the GPIO mode. The

silicon version of the 'STA111 is synthesized with shared GPIO on all three available LSPs. The silicon

version of the 'STA111 does not support dedicated GPIO.

Throughout this datasheet, notations exist to clarify the differences between features available on the Silicon

version and the HDL version.

KNOWN POWER-UP STATE

The 'STA111 has a known power-up condition. This is the same state that the device is in after a TRST reset.

This happens at power-up without the presence of a TCKB.

Reset can also occur via a 5 TMS high reset or a SOFTRESET command.

POWER-OFF HIGH IMPEDANCE INPUTS AND OUTPUTS

The 'STA111 backplane test port features power-off high impedance inputs and outputs.

The TDIB, TMSB, and TRSTB inputs have a 25KΩ pull-up resistor and no ESD clamp diode (ESD is controlled

with an alternate method). When the device is power-off (VDD floating), these inputs appear to be a capacitive

load to ground. When VDD = 0V (i.e.; not floating but tied to VSS) these inputs appear to be capacitive with the

pull-up to ground.

The TCKB input has no pull-up resistor and no ESD clamp diode (ESD is controlled with an alternate method).

When the device is power-off (VDD floating), the input appears to be a capacitive load to ground. When VDD = 0V

(i.e.; not floating but tied to VSS) the input appears to be a capacitive load to ground.

When the device is power-off (VDD = 0V or floating), the TDOB output appears to be a capacitive load.

TRST

TRSTB: Assertion of TRSTB will return the device back to its known power-up state.

TRSTn: TRSTn is an output on the LSP side of the 'STA111. While the LSP state-machine (level 2 protocol) is in

the Parked-TLR state the TRSTn pin will be driven low. In all other states the TRSTn pin will be driven

high.

PHYSICAL LAYER CHANGES

TRIST for TDOB and TDOn are signals for enabling an external buffer circuit between the 'STA111 and the

backplane/LSP. This would allow, for example, a CMOS-to-LVDS converter to drive an LVDS JTAG backplane

test bus. These signals are always driving. A separate TRIST is provided for each LSP to report a TRI-STATE on

TDO when the LSP is not in a shift state.

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