SCANSTA111 datasheet(24/38 Pages) TI

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SCANSTA111

SNLS060K – AUGUST 2001 – REVISED APRIL 2013

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LSP SHARED: In the shared mode of operation, the dot1 LSP pins TDIn, TDOn and TMSn pins become GPIO

pins. TMSn and TDOn are outputs, TDIn is an input in the GPIO mode.

The sequence of operations to use shared GPIOs on an LSP are as follows (example uses LSP0):

1. IR-Scan the 'STA111 address into the instruction register (address a 'STA111).

2. IR-Scan the MODESEL3 instruction into the instruction register to select Mode Register3 (Shared GPIO

configuration register) as the data register.

3. DR-Scan 00000001 into Mode Register3 to enable GPIOs on LSP0. The GPIOs will be enabled when the

TAP enters the RTI state at the end of this shift operation (TDO0 and TMS0 will be forced to logic 0 as

defined by the default value in the Shared GPIO Register0).

4. IR-Scan the SGPIO0 instruction into the instruction register to select the Shared GPIO Register0 as the data

5. DR-Scan 00000011 into the Shared GPIO Register0 to set TDO0 and TMS0 to a logic 1 (when TAP enters

Update-DR). During this operation, when the TAP enters Capture-DR, the present value on the TDI0 pin and

the values of TDO0 and TMS0 (as set by Shared GPIO Register0) will be captured into bits 2, 1 and 0 of the

shift register and will be scanned out 00000X00 (X = value present on TDI0 when TAP enters Capture-DR).

6. Step 5 can be repeated to generate waveforms on TDO0 and TMS0. If step 5 was repeated with 00000000

as data, TDO0 and TMS0 would be set to a logic 0 (when TAP state = Update-DR) and 00000X11 would be

scanned out (X = value present on TDI0 when TAP enters Capture-DR).

7. IR-Scan the GOTOWAIT or SOFTRESET instruction, or generate a TRSTB reset to disable the GPIOs.

ADDRESS INTERROGATION

The 'STA111 has four states that it can go to from the Wait-For-Address state: Unselected, Singularly-selected,

Multi/Broadcast-selected, and Address-interrogation (see Figure 13).

After a reset (or GOTOWAIT command) has been issued, the 'STA111 TAP is sequenced to the Capture-IR

state where XXXXXX01 is loaded into the shift register. Upon entering the Shift-IR state, the instruction register

is filled with the address interrogation value (3A hex) which is loaded into the address register as the TAP is

sequenced into the Update-IR state. On the next loop through Capture-IR the shift register is loaded with the

ones-complement of the slot address. In the Shift-IR state the address interrogation value is loaded into the

instruction register. The value presented on TDOB will be a wired-and address of all of the 'STA111s on the bus.

As this value is being shifted out, each 'STA111 will monitor its TDOB to see if it is receiving the same value it is

driving. If the device shifts all bits of its ones-complement address and never gets a compare error it will tri-state

TDOB and go to the Wait-For-Reset state. Alternately, if the device sees a compare error while it is shifting its

ones-complement address it will stop shifting its address and tri-state TDOB until the next shift operation; during

the next Shift-IR operation it will again try to present its address (if the previous instruction was 3A hex) while

monitoring TDOB.

Shifting 3A hex into the instruction registers of the 'STA111s will continue until all 'STA111s have presented their

address. At this time all devices will be waiting to be reset, and if a 3A is shifted into the 'STA111 instruction

registers the address read by the tester will be all weak 1s due to all TDOB's being tri-stated. Reading all ones

will signal the tester that address interrogation is complete. Since all ones signifies the end of Address-

Interrogation, no device can have an address of all zeros (ones-complement).

If at any time, during the address interrogation mode, any other instruction besides 3A hex is shifted into the

instruction register, then the 'STA111 will exit the interrogation mode. Also, the 'STA111's state machine will go

to the Wait-For-Address state.

This address interrogation scheme presumes that TDOB is capable of driving a weak 1 and that an 'STA111

driving a 0 will overdrive an 'STA111 driving a weak 1.

The following is an example of the Address-Interrogation function. Assume there are three 'STA111s (U1, U2 and

U3) on a dot1 backplane with slot addresses 010100, 100000 and 000001 respectively (assuming 6 address

pins).

1. The 'STA111s are reset and the interrogation address/op-code (3A hex) is shifted into the instruction

registers.

2. At the end of the instruction shift (Update-IR) the 'STA111 address registers are loaded with 3A hex.

3. The TAPs are sequenced to Capture-IR and the shift registers latch the ones-complement slot addresses

(U1=101011, U2=011111 and U3=111110).

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