TMS320C44 datasheet(2/52 Pages) TI

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TMS320C44

DIGITAL SIGNAL PROCESSOR

SPRS031C − AUGUST 1994 − REVISED MARCH 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

operation

The C44 has four on-chip communication ports for processor-to-processor communication with no external

hardware and simple communication software. This allows connectivity with no external-glue logic. The

communication ports remove input/output bottlenecks, and the independent smart 6-channel DMA

coprocessor is able to handle the CPU input/output burden.

To fit the C40 into a 304-pin PQFP package (thermally enhanced plastic quad flatpack), two communication

ports are removed and the external local and global address buses are reduced to 24 address lines each. In

this case, both the bond pads and driver circuits are removed, decreasing die size and power consumption.

Otherwise, functionality remains the same as the rest of the C4x family.

The communication-port token and data-strobe control lines are internally connected to avoid spurious data,

boot-up, and power consumption problems.

functions

This section lists signal descriptions for the C44 device: each signal, number of pins, operating mode(s) (that

is, input, output, or high-impedance state as indicated by I, O, or Z, respectively), and function. The signals are

grouped according to function.

Pin Functions

SIGNAL NAME

NO. OF

PINS

TYPE†

DESCRIPTION

GLOBAL-BUS EXTERNAL INTERFACE (73 pins)

D31−D0

I/O/Z

32-bit data port of the global-bus external interface

Data-bus-enable signal for the global-bus external interface

A23 −A0

O/Z

24-bit address port of the global-bus external interface

Address-bus-enable signal for the global-bus external interface

STAT3 −STAT0

Status signals for the global-bus external interface

LOCK

Lock signal for the global-bus external interface

STRB0‡

O/Z

Access strobe 0 for the global-bus external interface

R/ W0‡

O/Z

Read/ write signal for STRB0 accesses

PAGE0‡

O/Z

Page signal for STRB0 accesses

RDY0‡

Ready signal for STRB0 accesses

CE0‡

Control enable for the STRB0, PAGE0, and R/ W0 signals

STRB1‡

O/Z

Access strobe 1 for the global-bus external interface

R/ W1‡

O/Z

Read/ write signal for STRB1 accesses

PAGE1‡

O/Z

Page signal for STRB1 accesses

RDY1‡

Ready signal for STRB1 accesses

CE1‡

Control enable for the STRB1, PAGE1, and R/ W1 signals

LOCAL-BUS EXTERNAL INTERFACE (73 pins)

LD31−LD0

I/O/Z

32-bit data port of the local-bus external interface

LDE

Data-bus-enable signal for the local-bus external interface

LA23 −LA0

O/Z

24-bit address port of the local-bus external interface

LAE

Address-bus-enable signal for the local-bus external interface

LSTAT3 −LSTAT0

Status signals for the local-bus external interface

LLOCK

Lock signal for the local-bus external interface

† I = input, O = output, Z = high impedance

‡ The effective address range is defined by the local/global STRB ACTIVE bits in the memory interface-control registers.

TMS320C44 Datasheet(PDF) 2 Page - Texas Instruments

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