TMS320C44 datasheet(3/52 Pages) TI

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TMS320C44

DIGITAL SIGNAL PROCESSOR

SPRS031C − AUGUST 1994 − REVISED MARCH 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

Pin Functions (Continued)

SIGNAL NAME

DESCRIPTION

TYPE†

NO. OF

PINS

LOCAL-BUS EXTERNAL INTERFACE (73 pins) (Continued)

LSTRB0‡

O/Z

Access strobe 0 for the local-bus external interface

LR/ W0

O/Z

Read/ write signal for LSTRB0 accesses

LPAGE0

O/Z

Page signal for LSTRB0 accesses

LRDY0

Ready signal for LSTRB0 accesses

LCE0

Control enable for the LSTRB0, LPAGE0, and LR / W0 signals

LSTRB1‡

O/Z

Access strobe 1 for the local-bus external interface

LR/ W1

O/Z

Read/ write signal for LSTRB1 accesses

LPAGE1

O/Z

Page signal for LSTRB1 accesses

LRDY1

Ready signal for LSTRB1 accesses

LCE1

Control enable for the LSTRB1, LPAGE1, and LR/ W1 signals

COMMUNICATION PORT 1 INTERFACE (13 pins)

C1D7−C1D0

I/O

Communication port 1 data bus

CREQ1

I/O

Communication port 1 token-request signal

CACK1

I/O

Communication port 1 token-request-acknowledge signal

CSTRB1

I/O

Communication port 1 data-strobe signal

CRDY1

I/O

Communication port 1 data-ready signal

CDIR1

Communication port 1 direction signal

COMMUNICATION PORT 2 INTERFACE (13 pins)

C2D7−C2D0

I/O

Communication port 2 data bus

CREQ2

I/O

Communication port 2 token-request signal

CACK2

I/O

Communication port 2 token-request-acknowledge signal

CSTRB2

I/O

Communication port 2 data-strobe signal

CRDY2

I/O

Communication port 2 data-ready signal

CDIR2

Communication port 2 direction signal

COMMUNICATION PORT 4 INTERFACE (13 pins)

C4D7−C4D0

I/O

Communication port 4 data bus

CREQ4

I/O

Communication port 4 token-request signal

CACK4

I/O

Communication port 4 token-request-acknowledge signal

CSTRB4

I/O

Communication port 4 data-strobe signal

CRDY4

I/O

Communication port 4 data-ready signal

CDIR4

Communication port 4 direction signal

COMMUNICATION PORT 5 INTERFACE (13 pins)

C5D7−C5D0

I/O

Communication port 5 data bus

CREQ5

I/O

Communication port 5 token-request signal

CACK5

I/O

Communication port 5 token-request-acknowledge signal

CSTRB5

I/O

Communication port 5 data-strobe signal

CRDY5

I/O

Communication port 5 data-ready signal

CDIR5

Communication port 5 direction signal

† I = input, O = output, Z = high impedance

‡ The effective address range is defined by the local/global STRB ACTIVE bits in the memory interface-control registers.

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