TMS320F240 datasheet(65/105 Pages) TI

65 / 105 page

TMS320F240

DSP CONTROLLER

SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

CLOCK OPTIONS

clock options

PARAMETER

CLKMD[1:0]

Clock-in mode, divide-by-2

Clock-in mode, divide-by-1

PLL enabled, divide-by-2 before PLL lock

PLL enabled, divide-by-1 before PLL lock

timings with the PLL circuit disabled

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Input clock frequency, divide-by-2 mode

TA = –40°C to 125°C

0†

MHz

Input clock frequency, divide-by-1 mode

TA = –40°C to 125°C

0†

MHz

† This device utilizes a fully static design and, therefore, can operate with input clock cycle time [tc(CI)] approaching infinity. The device is

characterized at frequencies approaching 0 Hz.

switching characteristics over recommended operating conditions [H = 0.5 tc(CO)]

(see Note 1 and Figure 21)

PARAMETER

CLOCK MODE

MIN

TYP

MAX

UNIT

C cle time CPUCLK

CLKIN divide by 2

2tc(Cl)

†

tc(CPU)

Cycle time, CPUCLK

CLKIN divide by 1

tc(Cl)

C cle time SYSCLK

CPUCLK divide by 2

2tc(CPU)

†

tc(SYS)

Cycle time, SYSCLK

CPUCLK divide by 4‡

4tc(CPU)

C cle time CLKOUT

CLKIN divide by 2

2tc(Cl)

†

tc(CO)

Cycle time, CLKOUT

CLKIN divide by 1

tc(Cl)

†

td(CIH-CO)

Delay time, XTAL1/CLKIN high to CLKOUT high/low

tf(CO)

Fall time, CLKOUT

tr(CO)

Rise time, CLKOUT

tw(COL)

Pulse duration, CLKOUT low

H–10

H–6

H–1

tw(COH)

Pulse duration, CLKOUT high

H+0

H+4

H+8

† This device utilizes a fully static design and, therefore, can operate with input clock cycle time [tc(CI)] approaching infinity. The device is

characterized at frequencies approaching 0 Hz.

‡ SYSCLK is initialized to divide-by-4 mode by any device reset.

NOTE 1: Timings assume CLKOUT is set to output CPUCLK. CLKOUT is initialized to CPUCLK by power-on reset.

timing requirements over recommended operating conditions (see Figure 21)

CLOCK-IN MODE

MIN

MAX

UNIT

C cle time XTAL1/CLKIN

Divide by 2

†

tc(Cl)

Cycle time, XTAL1/CLKIN

Divide by 1

†

tf(Cl)

Fall time, XTAL1/CLKIN

tr(Cl)

Rise time, XTAL1/CLKIN

tw(CIL)

Pulse duration, XTAL1/CLKIN low as a percentage of tc(Cl)

tw(CIH)

Pulse duration, XTAL1/CLKIN high as a percentage of tc(Cl)

† This device utilizes a fully static design and, therefore, can operate with input clock cycle time [tc(CI)] approaching infinity. The device is

characterized at frequencies approaching 0 Hz.

TMS320F240 Datasheet(PDF) 65 Page - Texas Instruments

TMS320F240 Datasheet(HTML) 65 Page - Texas Instruments

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