TMS320F240 datasheet(19/105 Pages) TI

19 / 105 page

TMS320F240

DSP CONTROLLER

SPRS042E – OCTOBER 1996 – REVISED NOVEMBER 2002

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

reset (continued)

The occurrence of a reset condition causes the TMS320F240 to terminate program execution and affects

various registers and status bits. During a reset, RAM contents remain unchanged, and all control bits that are

affected by a reset are initialized to their reset state. In the case of a power-on reset, the PLL control registers

are initialized to zero. The program needs to recognize power-on resets and configure the PLL for correct

operation.

After a reset, the program can check the power-on reset flag (PORST flag, SYSSR.15), the illegal address flag

(ILLADR flag, SYSSR.12), the software reset flag (SWRST flag, SYSSR.10), and the watchdog reset flag

(WDRST flag, SYSSR.9) to determine the source of the reset. A reset does not clear these flags.

RS and PORESET must be held low until the clock signal is valid and VCC is within the operating range. In

addition, PORESET must be driven low when VCC drops below the minimum operating voltage.

hardware-generated interrupts

All the hardware interrupt lines of the DSP core are given a priority rank from 1 to 10 (1 being highest). When

more than one of these hardware interrupts is pending acknowledgment, the interrupt of highest rank gets

acknowledged first. The others are acknowledged in order after that. Of those ten lines, six are for maskable

interrupt lines (INT1–INT6) and one is for the nonmaskable interrupt (NMI) line. INT1–INT6 and NMI have the

priorities shown in Table 5.

Table 5. Interrupt Priorities at the Level of the DSP Core

INTERRUPT

PRIORITY AT THE

DSP CORE

RESET

TI RESERVED†

NMI

INT1

INT2

INT3

INT4

INT5

INT6

TI RESERVED†

† TI Reserved means that the address space is

reserved for Texas Instruments.

The inputs to these lines are controlled by the system module and the event manager as summarized in Table 6

and shown in Figure 5.

Table 6. Interrupt Lines Controlled by the System Module and Event Manager

PERIPHERAL

INTERRUPT LINES

System Module

INT1

INT5

INT6

NMI

Event Manager

INT2

INT3

INT4

TMS320F240 Datasheet(PDF) 19 Page - Texas Instruments

TMS320F240 Datasheet(HTML) 19 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL