EP2C50 datasheet(70/168 Pages) ALTERA

70 / 168 page

2–58

Altera Corporation

Cyclone II Device Handbook, Volume 1

February 2007

I/O Structure & Features

Figure 2–28. EP2C5 & EP2C8 I/O Banks

Notes (1), (2)

Notes to Figure 2–28:

(1)

This is a top view of the silicon die.

(2)

This is a graphic representation only. Refer to the pin list and the Quartus II software for exact pin locations.

(3)

The LVPECL I/O standard is only supported on clock input pins. This I/O standard is not supported on output

pins.

(4)

The differential SSTL-18 and SSTL-2 I/O standards are only supported on clock input pins and PLL output clock

pins.

(5)

The differential 1.8-V and 1.5-V HSTL I/O standards are only supported on clock input pins and PLL output clock

pins.

I/O Bank 2

I/O Bank 3

I/O Bank 4

I/O Bank 1

All I/O Banks Support

■ 3.3-V LVTTL/LVCMOS

■ 2.5-V LVTTL/LVCMOS

■ 1.8-V LVTTL/LVCMOS

■ 1.5-V LVCMOS

■ LVDS

■ RSDS

■ mini-LVDS

■ LVPECL (3)

■ SSTL-2 Class I and II

■ SSTL-18 Class I

■ HSTL-18 Class I

■ HSTL-15 Class I

■ Differential SSTL-2 (4)

■ Differential SSTL-18 (4)

■ Differential HSTL-18 (5)

■ Differential HSTL-15 (5)

I/O Bank 3

Also Supports the

3.3-V PCI & PCI-X

I/O Standards

I/O Bank 1

Also Supports the

3.3-V PCI & PCI-X

I/O Standards

Individual

Power Bus

I/O Bank 2 Also Supports

the SSTL-18 Class II,

HSTL-18 Class II, & HSTL-15

Class II I/O Standards

I/O Bank 4 Also Supports

the SSTL-18 Class II,

HSTL-18 Class II, & HSTL-15

Class II I/O Standards

EP2C50 Datasheet(PDF) 70 Page - Altera Corporation

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