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EP2C50 Datasheet(PDF) 36 Page - Altera Corporation |
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EP2C50 Datasheet(HTML) 36 Page - Altera Corporation |
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36 / 168 page  2–24 Altera Corporation Cyclone II Device Handbook, Volume 1 February 2007 Global Clock Network & Phase-Locked Loops Figure 2–15. LAB & I/O Clock Regions f For more information on the global clock network and the clock control block, see the PLLs in Cyclone II Devices chapter in Volume 1 of the Cyclone II Device Handbook. Column I/O Clock Region IO_CLK[5..0] Column I/O Clock Region IO_CLK[5..0] 6 6 I/O Clock Regions I/O Clock Regions 8 or 16 Global Clock Network Row I/O Clock Region IO_CLK[5..0] Cyclone Logic Array 6 6 LAB Row Clocks labclk[5..0] LAB Row Clocks labclk[5..0] LAB Row Clocks labclk[5..0] LAB Row Clocks labclk[5..0] LAB Row Clocks labclk[5..0] LAB Row Clocks labclk[5..0] 6 6 6 6 6 6 6 6 6 6 |
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