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AS3515 Datasheet(PDF) 45 Page - ams AG |
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AS3515 Datasheet(HTML) 45 Page - ams AG |
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45 / 67 page ![]() AS3515 V15 austriamicrosystems Data Sheet, Confidential www.austriamicrosystems.com Revision 3.1 44 - 66 Second Interrupt Register (26h) Table 45 IRQ_ENRD1 Register Bit Name Int. Type Description 7 JTEMP_high Level 1: Junction temperature has reached supervision level 6 LSP_overcurr Level 1: LSP output is in over-current off mode 5 HPH_overcurr Level 1: HPH output is in over-current off mode 4 I2S_status 1: LRCK of I2S interface is present 3 I2S_changed Status change 1: I2S LRCK clock was started or stopped, check I2S_status 2 MIC2_connect Level 1: Microphone was connected to MIC port 2 IRQ will be released after enabling the microphone stage. Detecting a microphone during operation has to be done by measuring the supply current. 1 MIC1_connect Level 1: Microphone was connected to MIC port 1 IRQ will be released after enabling the microphone stage. Detecting a microphone during operation has to be done by measuring the supply current. 0 HPH_connect Level 1: Headphone was connected to HHP port IRQ will be released after enabling the headphone output. Detecting a headphone during operation is not possible. The register is R/W; default value is 00h By writing to the register the corresponding interrupt is enabled, reading the register delivers the interrupt source. Third Interrupt Register (27h) Table 46 IRQ_ENRD2 Register Bit Name Int. Type Description 7..6 T_deb<1:0> - USB and charger de-bounce time control 00: 512ms 01: 256ms 10: 128ms 00: not defined 5 IRQ_Acthigh - 1: IRQ is active high 0: IRQ is active low 4 IRQ_PushPull - 1: IRQ output is push pull 0: IRQ output is open drain 3 Remote_Det2 Edge 1: Mic2 supply current got increased, Remote detection measure Mic2 supply current 2 Remote_Det1 Edge 1: Mic1 supply current got increased, Remote detection measure Mic1 supply current 1 RTC_update Edge 1: RTC timer IRQ occured 0 ADC_EndCon Edge 1: 8-bit ADC conversion completed The register is R/W; default value is 00h By writing to bit 0 to 3, the corresponding interrupt is enabled, reading these bits delivers the interrupt source. |
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